Generated reference › Exclude Data — Control Systems/Curve Fitting
kind: generated#block#control-systems-curve-fitting

Exclude Data — Control Systems/Curve Fitting

Control_Systems/Curve_Fitting/Exclude_Data · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Exclude Data

Control Systems / Curve Fitting

Marks the sample arriving now as one a downstream fit should ignore. The output is the flag itself: 1 when the sample is excluded and 0 when it is kept – the same polarity as the logical vector excludedata returns, so a script's outliers and this block's excl mean the same thing.

Four rules, and they are the whole of the MATLAB function: domain tests the predictor against a pair of bounds, range tests the response, box tests both, and indices tests the sample's position in the run. Feed the flag to a Switch to act on it, or to a Signal Recorder to count what a fit threw away.

Ports

  • x – the predictor, scalar. Read by domain and box; the other two rules ignore its value but still need the port wired.
  • y – the response, scalar. Read by range and box, and ignored by the other two in the same way.
  • excl – the flag, scalar: 1 excluded, 0 kept. Its size is fixed and follows neither input.

Parameters

  • Exclusion Rule – which test is applied. Four values, named as MATLAB names them:
    • domain – excluded when x < X₀ or x > X₁.
    • range – excluded when y < Y₀ or y > Y₁.
    • box – the default: excluded when either of the two above holds, i.e. when the pair falls outside the rectangle.
    • indices – excluded when the sample's one-based ordinal appears in Excluded Sample Indices. Neither input's value is read.
  • X Bounds – the pair [X₀ X₁] a predictor must stay inside, as a two-element row or column. Read by domain and box. Both comparisons are strict, so a sample exactly on a bound is kept.
  • Y Bounds – the pair [Y₀ Y₁] for the response, with the same shape and the same strictness. Read by range and box.
  • Excluded Sample Indices – the ordinals to exclude under indices, as a vector of whole numbers from 1 upwards; up to 64 of them, because the tests are unrolled at export. Duplicates and order do not matter, and an empty list excludes nothing.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.

The rule and its constants are structural and are inlined into the comparisons at export time rather than exposed as tunable parameters: the rule decides which comparisons the core contains at all, which no runtime parameter can do. Re-export after changing any of them.

The three HDL targets are genuine synthesizable Q16.16, and unusually cheaply so: nothing here is arithmetic on the signal, only comparisons against constants and an integer counter. One caveat follows from the format rather than from the block – a hardware port delivers a value already quantized to about 1.5×10−5, so a sample sitting within one quantum of a bound can fall on the other side of it there than in the simulation. It matters only for a bound a signal repeatedly lands exactly on.

Simulink bridge

None (Support::None). excludedata is a Curve Fitting Toolbox function, and that toolbox ships no Simulink library at all, so there is no path a diagram could name. The bridge reports this block rather than dropping it silently, and it therefore has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

  • Stateful, and discrete by nature (setDiscreteOnlyBlock(true)): the sample ordinal advances once per executed step.
  • The ordinal is one-based and counts this block's own steps, starting at 1 for the first. It advances under every rule, not only under indices, so switching rules renumbers nothing. A block given its own positive Sampling Time (s) counts its own ticks, not the solver's.
  • Both inputs are required under every rule. The port list is fixed when the block is built and cannot follow a configuration value, so domain still shows a y port and range still shows an x port. Wire the unread one to anything; its value is not read.
  • A bound pair is not checked for order. Giving X₀ > X₁ excludes every sample, which is what the two comparisons say and what MATLAB does with the same input.
  • It marks, it does not remove. A stream has no way to delete a sample – every block downstream still gets one value per step – so the flag is what a consumer acts on. That is also why the block pairs naturally with Switch.
  • Algebraic in its inputs. The flag depends only on the current x, y and ordinal; no past sample influences it.
  • No state space. The map is a comparison, not a linear system, so the block carries none and model reduction correctly declines to merge it.

Code facts#

FactValue
registered typeControl_Systems/Curve_Fitting/Exclude_Data
familyControl_Systems/Curve_Fitting
solver environment classICoreBlock_0_Control_Systems_1_Curve_Fitting_2_Exclude_Data
sourcesrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Curve_Fitting/Exclude_Data/ICoreBlock_0_Control_Systems_1_Curve_Fitting_2_Exclude_Data.cpp
headersrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Curve_Fitting/Exclude_Data/ICoreBlock_0_Control_Systems_1_Curve_Fitting_2_Exclude_Data.h
default size on canvas140 × 76 px
ports at insert2 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoublex
2inICoreDoubley
3outICoreDoubleexcl

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Exclusion Ruledomain%~%range%~%box%~%indices~~box—
X Bounds[-1 1]—
Y Bounds[-1 1]—
Excluded Sample Indices[10 20 30]—

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path—
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): marking samples a fit should ignore is a Curve Fitting Toolbox FUNCTION (excludedata), not a Simulink library block -- that toolbox ships no Simulink library at all -- so there is no path a diagram could name; the block is reported rather than dropped when a model crosses

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Exclude Data -- MATLAB's excludedata() on a stream, as a per-sample flag One output: 1 when the sample arriving now should be EXCLUDED from a downstream fit, 0 when it should be kept. That is the polarity of the logical vector excludedata() returns, and keeping it means a script's outliers and this block's excl mean the same thing.

⚠ THE FOUR RULES ARE THE WHOLE OF excludedata.m (R2026a) -- the rest of that file is argument handling, and these four lines are what it calls "HERE'S THE BEEF":

domain x < X0 or x > X1 range y < Y0 or y > Y1 box x < X0 or x > X1 or y < Y0 or y > Y1 indices the sample's one-based ordinal is one of the listed ones

⚠ THE RULE HAS ONE TEXTUAL FORM, ruleExpr() below, and all TEN generators read it, so a comparison cannot be right in nine backends and reversed in the tenth. compute_h carries the numeric twin, written in the same order with the same names.

⚠ BOTH COMPARISONS ARE STRICT, so a sample exactly ON a bound is KEPT. MATLAB writes < and >; a rule that excluded its own boundary would make a bound of [0, 0] reject the zeros.

⚠ THE ORDINAL COUNTS THIS BLOCK'S EXECUTED STEPS FROM 1, and it advances under every rule, not only under indices -- so changing the rule renumbers nothing. It is the block's only state, and it is why the block is discrete by nature.

⚠ GENUINE Q16.16 on the three HDL targets. Nothing here is arithmetic on the signal: four comparisons against constants inlined at export time, or an integer counter against a set of integers. The description carries the one caveat that follows from the format rather than from the block -- an HDL port delivers a value already quantized to about 1.5e-5, so a sample within one quantum of a bound can land on the other side of it there.

Sample results#

Exclude Data — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sampleExclude Data — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample-202012345t (s)in ICoreDouble-Out-0in ICoreDouble-Out-0out ICoreDouble-Out-0
tin ICoreDouble-Out-0in ICoreDouble-Out-0out ICoreDouble-Out-0
0-2-21
0.40.50.50
0.8-2-21
1.20.50.50
1.6-2-21
20.50.50
2.4-2-21
2.80.50.50
3.2-2-21
3.60.50.50
4-2-21
4.40.50.50
4.8-2-21
5.20.50.50

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0 … 0
rampRamp: slope 1 from t = 00 … 1
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias0 … 0
stepStep: 0 -> 1 at t = 1 s0 … 0

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit 3c100aff6f27235305db4ad4d572f32e342718ad · produced by docsSample --out <folder> --blocks Smooth Exclude_Data --steps 60 · data docs/generated/samples/Control_Systems__Curve_Fitting__Exclude_Data.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).