Varying Lowpass Filter — Control Systems/Continues
Control_Systems/Continues/Varying_Lowpass_Filter · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Varying Lowpass Filter
Control Systems / Continues
A Butterworth lowpass whose cutoff frequency is a signal rather than a setting, so the filter retunes continuously while the model runs. With d the monic normalized Butterworth coefficients (cutoff 1), the filter run at cutoff ω₀ is
H(s) = ω₀N ÷ (sN + dN−1·ω₀·sN−1 + … + d0·ω₀N)
The numerator is exactly the constant term of the denominator, so the DC gain is 1 at every cutoff – retuning moves the corner without moving the passband.
Ports
- u – the signal to filter. Scalar.
- w0 – ω₀, the cutoff in rad/s. Scalar, and expected positive: a negative cutoff mirrors the poles into the right half plane and the filter diverges.
- Output – y, the filtered signal, scalar.
Both inputs are scalars; a matrix signal is reported rather than filtered entry by entry, because each entry would need N states of its own.
Parameters
- Filter Order – N, the Butterworth order, a positive integer. It sets how sharply the filter rolls off (20·N dB per decade) and it is also the number of states, so changing it resizes the block's memory rather than merely retuning it.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The section coefficients are baked in at export time – they follow from the ORDER, which is structural – while the cutoff is read from its port every step. Integration is forward Euler at the block's period: the fixed-coefficient continuous blocks export an exact ZOH, but that needs a matrix exponential of a CONSTANT A, and here A moves every sample.
The cascade is emitted last section first in every target. That is not a style choice: each section's input is the previous section's state read before that section advances, and running backwards is what delivers it without a temporary per section. Emitted forwards, every section but the first would read a state that had already moved – one sample of lag each, which reads as wrong arithmetic rather than wrong timing.
Simulink bridge
Import and export, mapped to cstblocks/Linear Parameter Varying/Varying
Lowpass Filter – note the library is cstblocks, not the
"Control System Toolbox" display name, which add_block rejects.
"Filter Order" maps to N as a plain pass-through value, and it is
the block's only parameter; the cutoff travels on a port on both sides.
"Sampling Time (s)" does NOT cross – this Simulink block defines no
SampleTime parameter.
Notes
- Continuous and stateful: N states, all starting at zero, realized as a cascade of second-order sections in observer form (plus a first-order one for odd N) – the same realization the Simulink block integrates. On a filter whose cutoff is a SIGNAL that is a semantic choice, not a cosmetic one: this cascade and a single N-th order companion form have the same transfer function and agree exactly while the cutoff holds still, then diverge without bound once it moves.
- Strictly proper, so there is no direct feedthrough and the block CAN break an algebraic loop – unlike the Varying Notch Filter beside it, whose D is 1.
- Linear at any instant but not time-invariant, so it deliberately carries no state space; model reduction reports it as unmergeable.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Continues/Varying_Lowpass_Filter |
| family | Control_Systems/Continues |
| solver environment class | ICoreBlock_0_Control_Systems_1_Continues_2_Varying_Lowpass_Filter |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/Varying_Lowpass_Filter/ICoreBlock_0_Control_Systems_1_Continues_2_Varying_Lowpass_Filter.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/Varying_Lowpass_Filter/ICoreBlock_0_Control_Systems_1_Continues_2_Varying_Lowpass_Filter.h |
| default size on canvas | 120 × 90 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | w0 |
| 3 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Filter Order | 1 | N |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | cstblocks/Linear Parameter Varying/Varying Lowpass Filter |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Filter Order | N | passes through |
Caveat (shown to the user): the cutoff travels on a port on both sides, so only the order is a parameter; "Sampling Time (s)" does not cross, because this Simulink block defines no SampleTime parameter
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Varying Lowpass Filter — Butterworth of order N, cutoff arriving on a port A CASCADE OF OBSERVER-FORM SECTIONS — the realization the real R2026a block integrates. The Butterworth denominator splits into its conjugate-pair sections (plus the real pole for odd N); each pair is s^2 + a1*w0*s + w0^2 over w0^2, with a1 = 2*|Re(p)| and a0 exactly 1:
first order (odd N, always first): dz = w0*(in - z), out = z second order: dz1 = -a1*w0*z1 + z2 dz2 = -w0^2*z1 + w0^2*in, out = z1
chained first-order first, then the pairs ascending in a1, each section's input being the previous one's output taken PRE-update. y is the last section's z1 — no w0^N scaling, since every section already carries its own numerator.
⚠ NOT the single Nth-order companion form this block first shipped with. Same transfer function, and identical output while w0 holds still — which is why export verification passed it 10/10 while Simulink parity failed at 1.05. See the header for the two traps.
See the header for the numeric evidence that the Simulink block really is Butterworth, and for why the block carries a state but no state space.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.06344 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.622 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 4.159 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | 0.4428 … 5.361 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Continues__Varying_Lowpass_Filter.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).