Variable Time Delay — Control Systems/Continues

Variable Time Delay

Control Systems / Continues

Delays the input by an amount that is itself a signal, applied as of now:

y(t) = u(t − d(t))

Whatever the delay port reads at time t is how far back the block reaches on that tick. The delay is given in seconds and rounded to a whole number of samples, so a delay of zero is direct feedthrough.

This is the "variable time delay" reading of a moving delay. Its sibling, Variable Transport Delay, takes the same port to mean a transit rate and integrates it instead; the two agree exactly while the delay is constant and diverge as soon as it moves. Pick this block when the delay is simply "how stale the signal is right now", and that one when you are modelling material carried down a pipe at a varying speed.

Ports

• u – the delayed signal, of any size [m,n]. This is what comes out delayed.
• d – the delay in seconds, a scalar [1,1]. It applies to the whole signal, not per entry. Negative values are clamped to zero – nothing arrives before it was sent – and values beyond Maximum Delay (s) are clamped to it.
• Output – the delayed signal, the SAME size [m,n] as u.

Parameters

• Maximum Delay (s) – scalar, the longest delay the block can represent, in seconds. Defaults to 10, matching Simulink. It sets the depth of the transit line: a requested delay beyond it is clamped rather than growing the buffer, because a line that reallocates mid-run is a latency spike on a real target. Cost is proportional – at a 0.01 s rate the default is 1000 stored samples per signal entry – so set it to the largest delay you actually need rather than leaving headroom.
• Initial Output – scalar, what the block emits while the delay still reaches back past the start of the run. Defaults to 0. The whole buffer is pre-filled with it, so a run starts from a defined line rather than from samples that were never taken.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the resolution the delay is rounded to, and the unit the maximum delay is counted in, so it is part of the arithmetic and not merely a schedule.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries the ring buffer as its state, pre-filled with the initial output, and indexes it with the rounded delay exactly as the simulation does. Only 1/dt and the depth are baked in as constants; the delay itself is read from its port every tick.

The three HDL targets carry the line as a slot × element register file and derive the read address in hardware, using the generated fixed-point package's fx_to_int – an arithmetic shift by the fraction width, which is floor() and so rounds the same way the software targets do. A zero delay is special-cased to the input rather than read back from the buffer: the write is registered, so on that tick the addressed slot still holds its previous contents, and reading it would return the value from a whole lap ago instead of the sample just written. Note that the register file is sized from Maximum Delay (s), so a generous bound is paid for in flip-flops – keep it tight for a synthesizable core.

Note that on the HDL targets the delay arrives already quantized to the Q-format, one quantum being about 1.5×10⁻⁵. A requested delay sitting within that of a half-sample boundary can round to a neighbouring sample count there but not on the software targets. That is inherent to carrying a time in fixed point, not a defect of the generated core; keep the delay away from exact half-sample values if it matters.

Simulink bridge

Import and export, mapped to simulink/Continuous/Variable Time Delay. "Maximum Delay (s)" to MaximumDelay, "Initial Output" to InitialOutput. The block always implies VariableDelayType = "Variable time delay" – that parameter is the only thing distinguishing this Simulink block from Variable Transport Delay, which shares its BlockType – and PadeOrder = 0, since the delay is realized as a true transit line and never as a Padé approximation. A Simulink block carrying either at a different value is reported on import rather than silently accepted.

This block has no SampleTime parameter in Simulink – it is a continuous block there – so "Sampling Time (s)" stays on the ICore side and does not cross.

Simulink's block is continuous and interpolates between stored points, while this one rounds to whole samples. The two agree exactly when the delay is a whole multiple of the step size, and differ by up to half a sample when it is not.

Notes

• Stateful: Maximum Delay / dt + 1 past values of the signal port.
• Discrete by nature – the line advances one slot per sample, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
• The delay is rounded to whole samples, so sub-sample delay is not interpolated. Shorten the sampling time for finer resolution.
• Not linear in the state-space sense, and so deliberately carries no state space: a pure delay is the transcendental factor e^(−sd), which no finite A/B/C/D expresses, and a time-varying one is not even time-invariant.