State Space — Control Systems/Continues
Control_Systems/Continues/State_Space · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
State Space
Control Systems / Continues
A continuous-time linear system in state-space form:
dx/dt = A·x + B·u
y = C·x + D·u
with n states, m inputs and p outputs, so A is [n,n], B is [n,m], C is [p,n] and D is [p,m].
Ports
- Input – the input vector u, [m,1].
- Output – the output vector y, [p,1], sized from C.
Parameters
- A, B, C, D – the system matrices. Their dimensions must agree with each other and with the connected input; a mismatch stops the run with a message naming the block.
- Initial State Vector – x at the start of the run, [n,1].
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. A deployable target runs a discrete model, so the export carries this system discretized by the run's method and the generated code matches the in-app simulation.
Simulink bridge
Import and export, mapped to simulink/Continuous/State-Space.
"A", "B", "C", "D" to A, B, C,
D; "Initial State Vector" to X0; "Sampling Time (s)"
to SampleTime. Nothing is left behind – every parameter has a
counterpart.
Notes
- Stateful and continuous: the solver integrates the state between steps.
- Being linear, the block is directly usable by the model reduction and linear-analysis commands.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Continues/State_Space |
| family | Control_Systems/Continues |
| solver environment class | ICoreBlock_0_Control_Systems_1_Continues_2_State_Space |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/State_Space/ICoreBlock_0_Control_Systems_1_Continues_2_State_Space.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/State_Space/ICoreBlock_0_Control_Systems_1_Continues_2_State_Space.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
A | [0 1;-1 -1] | A |
B | [0; 1] | B |
C | [1 0] | C |
D | [0] | D |
Initial State Vector | [0; 0] | X0 |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Continuous/State-Space |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
A | A | passes through |
B | B | passes through |
C | C | passes through |
D | D | passes through |
Initial State Vector | X0 | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Continuous State Space block — MIMO realization A linear MIMO system dx/dt = A x + B u, y = C x + D u (A:[n,n] B:[n,m] C:[p,n] D:[p,m]). The input port is the [m,1] input vector u, the output port the [p,1] output vector y, and the block state is the [n,1] vector x (NOT an element-wise [n,K] like the Transfer Function block — here the vector IS the MIMO signal, there is no per-entry replication).
Simulation: compute_f/compute_h run the state-space products on the continuous SS; the solver integrates dx/dt with RK. compute_f_discrete/compute_h_discrete run the recursion on the discretized SS. Initial state comes from the "Initial State Vector" config.
Code export (Python/MATLAB/Java/Rust/C/C++ and HDL/PLC) Targets cannot integrate a continuous ODE, so every generator realizes the DISCRETIZED state-space recursion directly — structurally identical to the in-app discrete simulation: y[k] = C x[k] + D u[k] (output from the CURRENT state) x[k+1] = A x[k] + B u[k] (state update; uses the same x[k]) A,B,C,D are embedded as constants (B=Bu, D=Du to match the simulation exactly) and x is the only persistent state, seeded with the configured initial state. ssDiscreteExport() discretizes then hands back A,B,C,D,x0; see per-language sections below.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.008893 … 0.05458 |
ramp | Ramp: slope 1 from t = 0 | 0 … 4.847 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.3041 … 0.4966 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.162 … 0.4821 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Continues__State_Space.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).