Entity Transport Delay — Control Systems/Continues
Control_Systems/Continues/Entity_Transport_Delay · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Entity Transport Delay
Control Systems / Continues
Transports a signal across a delay that can change while the run is in progress – a conveyor, a pipeline, a transmission line, anything whose transit time is itself a signal:
y(t) = u(t − d(t))
The delay arrives on its own port in seconds and is rounded to a whole number of samples, so a delay of zero is direct feedthrough. Values are held in a ring buffer whose depth is set by Capacity (samples); a delay longer than that is clamped to it, and a delay reaching back past the start of the run reads the configured Initial Output.
Ports
- u – the transported signal, of any size [m,n]. This is what comes out delayed.
- d – the transit time in seconds, a scalar [1,1]. It applies to the whole signal, not per entry. Negative values are clamped to zero – nothing arrives before it was sent.
- Output – the delayed signal, the SAME size [m,n] as u.
Parameters
- Initial Output – scalar, what the block emits while the delay still reaches back past the start of the run. Defaults to 0. The whole buffer is pre-filled with it, so a run starts from a defined line rather than from samples that were never taken.
- Capacity (samples) – the depth of the ring buffer, and so the longest delay the block can represent, in samples. Defaults to 64 – at a 0.01 s period that is 0.64 s of transit. A requested delay beyond it is clamped rather than growing the buffer, because a transit line that reallocates mid-run is a latency spike on a real target.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the resolution the delay is rounded to, and the unit the capacity is counted in, so it is part of the arithmetic and not merely a schedule.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries the ring buffer as its state, pre-filled with the initial output, and indexes it with the rounded delay exactly as the simulation does. Only 1/dt is baked in as a constant; the delay itself is read from its port every tick.
The three HDL targets carry the line as a slot × element register
file and derive the read address in hardware, using the generated fixed-point
package's fx_to_int – an arithmetic shift by the fraction
width, which is floor() and so rounds the same way the software targets do.
A zero delay is special-cased to the input rather than read back from the buffer:
the write is registered, so on that tick the addressed slot still holds its
previous contents, and reading it would return the value from a whole lap ago
instead of the sample just written.
Note that on the HDL targets the delay arrives already quantized to the Q-format, one quantum being about 1.5×10−5. A requested delay sitting within that of a half-sample boundary can round to a neighbouring sample count there but not on the software targets. That is inherent to carrying a time in fixed point, not a defect of the generated core; keep the delay away from exact half-sample values if it matters.
Simulink bridge
No equivalent – the block does not cross in either direction.
Simulink's Entity Transport Delay is a SimEvents block: it
transports discrete entities – individual items that queue, occupy
capacity and depart – and its ports carry an entity stream, not a signal.
ICore's library is signal-flow throughout, so there is nothing to map the entity
domain onto, and its Capacity parameter counts a population of
entities rather than the ring-buffer depth this block calls by that name.
Exchanging the two would silently substitute one meaning for the other, so the
bridge reports this block instead. If what you need is a signal-domain
transport delay that DOES cross, Simulink's own
simulink/Continuous/Transport Delay is the counterpart to ask for.
Notes
- Stateful: capacity + 1 past values of the signal port.
- Discrete by nature – the line advances one slot per sample, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
- The delay is rounded to whole samples, so sub-sample transit is not interpolated. Shorten the sampling time for finer resolution.
- Not linear in the state-space sense, and so deliberately carries no state space: a pure delay is the transcendental factor e^(−sd), which no finite A/B/C/D expresses, and a time-varying one is not even time-invariant.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Continues/Entity_Transport_Delay |
| family | Control_Systems/Continues |
| solver environment class | ICoreBlock_0_Control_Systems_1_Continues_2_Entity_Transport_Delay |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/Entity_Transport_Delay/ICoreBlock_0_Control_Systems_1_Continues_2_Entity_Transport_Delay.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/Entity_Transport_Delay/ICoreBlock_0_Control_Systems_1_Continues_2_Entity_Transport_Delay.h |
| default size on canvas | 110 × 80 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | d |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Output | 0 | not crossed |
Capacity (samples) | 64 | not crossed |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| deliberately not crossed | Initial Output, Capacity (samples) |
Caveat (shown to the user): Simulink's Entity Transport Delay is a SimEvents block: it transports discrete ENTITIES - items that queue, occupy capacity and depart - and its ports carry an entity stream rather than a signal. ICore's library is signal-flow throughout, so there is no entity domain to map onto, and Simulink's Capacity counts a population of entities rather than the ring-buffer depth this block calls by that name. Exchanging the two would substitute one meaning for the other silently. For a signal-domain transport delay that does cross, simulink/Continuous/Transport Delay is the counterpart
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Entity Transport Delay block — y(t) = u(t - d(t)), a signal-domain transit line WHAT THIS BLOCK IS, AND WHAT SIMULINK'S IS NOT. Simulink's Entity Transport Delay (BlockType EntityTransportDelay, in the Continuous library) is a SimEvents block: it transports discrete ENTITIES - individual items with attributes, which queue, occupy capacity and depart - and its two inputs are an entity stream and a delay signal. ICore's library is signal-flow throughout: every port carries an ICoreDouble matrix, and there is no entity domain to map onto. This block is therefore the signal-domain analogue, keeping the Simulink block's shape (a signal in, a delay in, one out) and the transit it models:
y(t) = u(t - d(t))
with the delay arriving on its own port in SECONDS and rounded to whole samples. That is a faithful analogue of transit time, but it is NOT entity transport: there are no entities to count, nothing queues, and "capacity" here bounds a ring buffer rather than a population. The Simulink catalog entry is registered Support::None for exactly that reason, so the bridge reports the block instead of silently exchanging something that does not correspond.
Implementation: a ring buffer of capacity+1 past values, all pre-filled with the configured initial output so a delay reaching past the start of the run reads that rather than a zero that was never sampled. buffer[head] = u (the current sample) k = clamp(round(d / dt), 0, capacity) y = buffer[(head - k + capacity + 1) mod (capacity + 1)] head = (head + 1) mod (capacity + 1) k = 0 is direct feedthrough, which is what a zero delay should be.
Discrete by nature: the line advances one slot per SAMPLE, so dt is the block's own rate.
Code export: seven of the ten targets. The three HDL backends are deliberately unsupported -- see the note above generateDeclCode_PLC_ST and the description's "Code export" section.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Continues__Entity_Transport_Delay.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).