Sum — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Sum · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Sum
Control Systems / Base Blocks
Adds its inputs entry by entry, each one taken with its own sign. Any number of inputs is allowed, and every input carries either a plus or a minus.
Ports
- Inputs – two by default, and the count is user-editable. All of them must carry the same signal size.
- Output – the signed sum, of that same size.
Signs
An input's sign is its port description label, not a parameter: click the label on the canvas and type + or -. A blank label counts as +. New ports start at +. Because the sign lives on the port, it travels with copy, undo and save, and can never fall out of step with the port count.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The signs are fixed into the generated arithmetic at export time.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Sum. There is no
parameter behind the signs on either side: the port labels become Simulink's
Inputs sign string (++-), and an imported sign string
becomes this port list. "Sampling Time (s)" goes to SampleTime, as
on every block.
Notes
- Algebraic, with no state.
- Subtract is the same block with its second input pre-negated.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Sum |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sum |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Sum/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sum.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Sum/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sum.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | SIGN_PLUS |
| 2 | in | ICoreDouble | SIGN_PLUS |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Sum |
| port-count rule | PortsParam::SumSigns |
SampleTime parameter | yes |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 3 ports (2 in, 1 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | -4 |
| 0.4 | 0.5 | 0.5 | 1 |
| 0.8 | -2 | -2 | -4 |
| 1.2 | 0.5 | 0.5 | 1 |
| 1.6 | -2 | -2 | -4 |
| 2 | 0.5 | 0.5 | 1 |
| 2.4 | -2 | -2 | -4 |
| 2.8 | 0.5 | 0.5 | 1 |
| 3.2 | -2 | -2 | -4 |
| 3.6 | 0.5 | 0.5 | 1 |
| 4 | -2 | -2 | -4 |
| 4.4 | 0.5 | 0.5 | 1 |
| 4.8 | -2 | -2 | -4 |
| 5.2 | 0.5 | 0.5 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 2 |
ramp | Ramp: slope 1 from t = 0 | 0 … 11.6 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -2 … 1.999 |
step | Step: 0 -> 1 at t = 1 s | 0 … 2 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Sum.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).