Signed Sqrt — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Signed_Sqrt · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Signed Sqrt
Control Systems / Base Blocks
Takes the square root of the input's magnitude and gives it back the input's sign, entry by entry: y = sign(u)·√|u|. It is the square root extended to negative inputs, and the only form of it that is defined for every real input – there are no out-of-domain values and no NaN.
Ports
- Input – the signal u, of any size [m,n]. Every real value is in domain.
- Output – the signed root y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to expose as a tunable parameter: the operation is the block, so it is emitted straight into the arithmetic.
The seven software targets agree exactly, on every real input. The sign is
carried by an explicit test on u < 0 rather than by a
sign() function, because Java's Math.signum and Rust's
f64::signum answer ±1 at ±0.0 and would turn
√0 into a signed zero the C++ reference does not produce.
The three HDL targets are simulation-only. There is no square root in
the Q16.16 datapath to call, so the generated cores convert at the port boundary
and evaluate the root in real arithmetic – correct in
simulation, but not offered as synthesizable. They carry no NaN, which costs
nothing here: this block has no out-of-domain values to represent.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Signed Sqrt.
That library entry is Simulink's Sqrt block pre-set to
Operator = signedSqrt, so the entry writes that
Operator as a fixed parameter – it has no ICore config behind
it, because this block offers no choice of operator. An imported block whose
Operator says anything else is reported rather than silently
accepted. "Sampling Time (s)" maps to SampleTime, as on every
block.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- ICore's Sqrt block offers this same operator alongside the plain and reciprocal roots. Use that one to switch between them on a single block; use this one when the operation is fixed, and to round-trip Simulink's own Signed Sqrt library entry.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Signed_Sqrt |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Signed_Sqrt |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Signed_Sqrt/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Signed_Sqrt.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Signed_Sqrt/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Signed_Sqrt.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Signed Sqrt |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | Operator = signedSqrt |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Signed Sqrt block -- the square root extended to negative inputs y = sign(u) * sqrt(|u|), entry by entry. Algebraic and stateless, no state space (the root is not linear). It is the one root with NO out-of-domain values: |u| is never negative, so every real input has a real answer and the ten targets never have to agree on a NaN.
RELATIONSHIP TO THE Sqrt BLOCK. Simulink's Signed Sqrt is its Sqrt block pre-set to Operator = signedSqrt, and ICore's Sqrt offers that operator too, so the arithmetic here is deliberately identical to that block's SignedSqrt branch. What this block adds is the BRIDGE IDENTITY: it maps to simulink/Math Operations/Signed Sqrt, so a model containing that library entry imports as the same block it left as, instead of collapsing into a general Sqrt whose Operator a later edit could silently change.
HDL. Q16.16 has no square root to call, so the three HDL backends are SIMULATION-ONLY: they convert at the port boundary and evaluate the root in
real. Unlike the plain and reciprocal roots they need no out-of-domain guard for correctness -- the root is taken of a magnitude -- but math_real.sqrt still asserts on a negative argument, so the branch is written to hand it |u| either way.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -1.414 |
| 0.4 | 0.5 | 0.7071 |
| 0.8 | -2 | -1.414 |
| 1.2 | 0.5 | 0.7071 |
| 1.6 | -2 | -1.414 |
| 2 | 0.5 | 0.7071 |
| 2.4 | -2 | -1.414 |
| 2.8 | 0.5 | 0.7071 |
| 3.2 | -2 | -1.414 |
| 3.6 | 0.5 | 0.7071 |
| 4 | -2 | -1.414 |
| 4.4 | 0.5 | 0.7071 |
| 4.8 | -2 | -1.414 |
| 5.2 | 0.5 | 0.7071 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 2.408 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9998 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Signed_Sqrt.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).