Real Imag To Complex — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Real_Imag_To_Complex · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Real-Imag to Complex
Control Systems / Base Blocks
Makes a complex signal from its real and imaginary parts, entry by entry: y = re + j·im. Either part can be a constant instead of an input, which is how a real signal becomes a complex one.
Ports
- Re – the real part, of any size [m,n]. With Input set to Imag this one port is the imaginary part instead, and the real part is Constant Part.
- Im – the imaginary part, of any size [m,n], present only with Input set to Real and imag. With Real or Imag the block has ONE input. The ports are added and removed by hand: the run stops, naming the block, when their count does not match Input.
- Output – the complex signal y, of size [m,n]. A scalar part
expands over the other one; two parts of different sizes, neither of them
scalar, are refused. The port carries the type ICoreComplex (badge
cplx), and only a block that reads complex values takes it – Complex to Real-Imag takes it apart again.
Parameters
- Input – Real and imag (both parts are inputs, the default), Real (the input is the real part) or Imag (the input is the imaginary part).
- Constant Part – the part that is not an input, used with Real or Imag: a scalar, or a matrix the size of the input. Default 0.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. A complex signal is stored as its two parts side by
side in the target's own numbers – element k's real part, then its
imaginary part, the layout of Simulink Coder's creal_T arrays
– so the block is a copy into that layout and does no arithmetic. The
three HDL targets are therefore fully synthesizable; each part is
a Q16.16 value there, as every signal is.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Real-Imag to
Complex. "Input" ↔ Input (the same three choices),
"Constant Part" ↔ ConstantPart and "Sampling Time (s)" ↔
SampleTime. Setting Input moves Simulink's ports, and
an imported block takes the port count it implies.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Each part is real: a complex signal is taken apart with Complex to Real-Imag first.
- No state space: its output is complex, and model reduction is real.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Real_Imag_To_Complex |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Real_Imag_To_Complex |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Real_Imag_To_Complex/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Real_Imag_To_Complex.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Real_Imag_To_Complex/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Real_Imag_To_Complex.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | Re |
| 2 | in | ICoreDouble | Im |
| 3 | out | ICoreSignalType::COMPLEX_ID | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Input | Real and imag%~%Real%~%Imag~~Real and imag | Input |
Constant Part | 0 | ConstantPart |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Real-Imag to Complex |
| port-count rule | PortsParam::RealImagInputs |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Input | Input | Real and imag → Real and imag, Real → Real, Imag → Imag |
Constant Part | ConstantPart | passes through |
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Real-Imag to Complex block -- a complex signal from its two parts y = re + j*im, entry by entry. Simulink's RealImagToComplex: Input chooses which parts are inputs -- both, or one with the other a constant ("Constant Part") -- and a scalar part expands over a matrix one (measured on R2026a: [1 2 3] with 5 is [1+5i 2+5i 3+5i], and a scalar with a [1 2] constant is [4+7i 4+8i]; two different non-scalar sizes are refused).
The output is an ICoreComplex port (FEATURES_TO_ADD.md BF23.1), so its matrix is r x 2c for an [r, c] signal: column 2k holds element k's real part and column 2k+1 its imaginary part, the layout of Simulink Coder's creal_T arrays. Every target therefore stores the result in the doubles it already stores, and this block is a strided copy in all ten of them -- no arithmetic at all, so the three HDL targets are fully synthesizable.
The input list follows Input, as Simulink's does: two ports for "Real and imag", one for the others. The ports are edited by hand, as Send's enable is, and the build checks the count against the choice.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.