Mux — Control Systems/Base Blocks

Mux

Control Systems / Base Blocks

Combines several input signals into one wider signal by stacking them vertically, in port order. A [2,1] and a [3,1] input become a single [5,1] output.

Ports

• Inputs – two by default, and the count is user-editable. At least two are required. They may differ in row count but must all agree in column count.
• Output – the stack: as many rows as all inputs together, and the inputs' shared column count.

Parameters

• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The stack is unrolled at export time, so the generated code is plain assignment with no loop over ports.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/Mux. There is no parameter behind the width on either side: the port count becomes Simulink's Inputs number, and an imported count becomes this port list.

"Sampling Time (s)" does not cross. Simulink's Mux is a virtual block with no SampleTime parameter at all, so a Mux configured here with an explicit rate reports that the rate stayed on the ICore side.

Simulink's Bus Creator imports as this block when nothing reads it as a bus. A block that reads a bus as a vector sees the stacked column this block builds, and the two were measured to be the same function: a Bus Creator of (1, [2 3], 4) read through Bus to Vector answers [1 2 3 4], and a Mux of the same three inputs answers [1 2 3 4]. Nothing is preset on the fold, the two dialogs agreeing on both shared fields. A Bus Creator that a Bus Selector reads imports as ICore's Bus Creator instead, because a Bus Selector picks an element by name, which a Mux does not have. Simulink itself refuses a Mux into a Bus Selector. A Bus Creator imported as a Mux re-exports as a Mux, the same stack under a different palette entry. Simulink's three bus-TYPE fields (OutDataTypeStr, NonVirtualBus, InheritFromInputs) have no counterpart here and are reported rather than dropped quietly.

Notes

• Algebraic, with no state – pure signal routing, nothing is scaled or reordered.
• The output size is derived from the inputs, so it is only settled once the upstream blocks have resolved theirs.