Mux — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Mux · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Mux
Control Systems / Base Blocks
Combines several input signals into one wider signal by stacking them vertically, in port order. A [2,1] and a [3,1] input become a single [5,1] output.
Ports
- Inputs – two by default, and the count is user-editable. At least two are required. They may differ in row count but must all agree in column count.
- Output – the stack: as many rows as all inputs together, and the inputs' shared column count.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The stack is unrolled at export time, so the generated code is plain assignment with no loop over ports.
Simulink bridge
Import and export, mapped to simulink/Signal Routing/Mux. There is no
parameter behind the width on either side: the port count becomes Simulink's
Inputs number, and an imported count becomes this port list.
"Sampling Time (s)" goes to SampleTime, as on every block.
Notes
- Algebraic, with no state – pure signal routing, nothing is scaled or reordered.
- The output size is derived from the inputs, so it is only settled once the upstream blocks have resolved theirs.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Mux |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Mux |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Mux/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Mux.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Mux/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Mux.h |
| default size on canvas | 20 × 60 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | in | ICoreDouble | — |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Mux |
| port-count rule | PortsParam::MuxCount |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 3 ports (2 in, 1 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [2x1] entry 0 |
|---|---|---|---|
| 0 | -2 | -2 | [-2, -2] |
| 0.4 | 0.5 | 0.5 | [0.5, 0.5] |
| 0.8 | -2 | -2 | [-2, -2] |
| 1.2 | 0.5 | 0.5 | [0.5, 0.5] |
| 1.6 | -2 | -2 | [-2, -2] |
| 2 | 0.5 | 0.5 | [0.5, 0.5] |
| 2.4 | -2 | -2 | [-2, -2] |
| 2.8 | 0.5 | 0.5 | [0.5, 0.5] |
| 3.2 | -2 | -2 | [-2, -2] |
| 3.6 | 0.5 | 0.5 | [0.5, 0.5] |
| 4 | -2 | -2 | [-2, -2] |
| 4.4 | 0.5 | 0.5 | [0.5, 0.5] |
| 4.8 | -2 | -2 | [-2, -2] |
| 5.2 | 0.5 | 0.5 | [0.5, 0.5] |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Mux.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).