Gain — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Gain · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Gain
Control Systems / Base Blocks
Multiplies the input signal by a constant gain K. The gain may be a scalar or a matrix, and the multiplication type decides how it meets the input: entry by entry, or as a matrix product from either side.
Ports
- Input – the signal to scale, of any size [m,n].
- Output – the scaled signal. Element-wise keeps the input shape; a matrix product [m,n]×[n,p] gives [m,p], so a matrix gain may change the signal dimensions.
Parameters
- Gain Value – scalar or matrix. A scalar is expanded in every mode, so the block computes y = k·u whatever the multiplication type.
- Multiplication Type
- Element-wise (K.*u) – entry by entry. A scalar on either side expands to the other's shape.
- Matrix (K*u) – the gain multiplies from the left.
- Matrix (u*K) – the gain multiplies from the right.
- Matrix (K*u) (u vector) – the input is taken as a vector of either orientation, reshaped to a column, and the result is a column.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The gain is exposed as a tunable parameter on the generated core rather than inlined into the arithmetic.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Gain.
"Gain Value" to Gain; "Multiplication Type" to
Multiplication, one option for one option, so that round trip is
lossless; "Sampling Time (s)" to SampleTime, as on every block.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Model reduction can absorb the block only when the gain acts from the left (y = D·u). Matrix (u*K), and element-wise with a matrix gain, have no such form and are reported as unmergeable.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Gain |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Gain |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Gain/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Gain.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Gain/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Gain.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Gain Value | 1 | Gain |
Multiplication Type | Element-wise (K.*u)%~%Matrix (K*u)%~%Matrix (u*K)%~%Matri… | Multiplication |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Gain |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Gain Value | Gain | passes through |
Multiplication Type | Multiplication | Element-wise (K.*u) → Element-wise(K.*u), Matrix (K*u) → Matrix(K*u), Matrix (u*K) → Matrix(u*K), Matrix (K*u) (u vector) → Matrix(K*u) (u vector) |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Gain.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).