Divide — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Divide · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Divide
Control Systems / Base Blocks
Combines its inputs entry by entry, each one either multiplying or dividing: y = u₁ · u₂ ÷ u₃ … Any number of inputs is allowed, and every input carries either a * or a /. A leading / is a reciprocal, so a /* port list computes (1/u₁)·u₂.
Ports
- Inputs – two by default, and the count is user-editable. All of them must carry the same signal size; this block does not expand a scalar over a matrix.
- Output – the combined signal, of that same size.
Operations
An input's operation is its port description label, not a parameter: click the label on the canvas and type * or /. A blank label counts as *. A fresh block comes up as * then /, matching Simulink's default. Because the operation lives on the port, it travels with copy, undo and save, and can never fall out of step with the port count – the same arrangement Sum uses for its signs.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The operations are fixed into the generated arithmetic at export time; there is nothing left to retune on the generated core.
The seven software targets divide in IEEE double precision and agree exactly, including division by zero, which gives ±Inf (or NaN for 0/0) in all seven.
The three HDL targets are simulation-only. Q16.16 fixed point cannot
hold a quotient whose divisor has come near zero – one quantum of the
divisor is 1.5×10⁻⁵, so an ordinary signal crossing zero
produces a result far outside the format – so the generated cores convert
at the port boundary and evaluate in real arithmetic. They are
correct in simulation but are not offered as synthesizable, and having no
infinity they answer 0 where a divisor is exactly zero.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Divide. There is
no parameter behind the operations on either side: the port labels become
Simulink's Inputs string (*/), and an imported string
becomes this port list. Simulink's Multiplication is always written
as Element-wise(.*), which is what this block computes; the matrix
form has no counterpart here. "Sampling Time (s)" goes to
SampleTime, as on every block.
Notes
- Algebraic, with no state.
- Not linear – a product of two signals is not, and nor is a quotient – so the block deliberately carries no state space and model reduction reports it as unmergeable. Gain is the linear sibling, a signal times a constant, and that one can be absorbed.
- At least two inputs are required, as for Sum. A pure reciprocal is a two-input block with a constant on the first port.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Divide |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Divide |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Divide/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Divide.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Divide/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Divide.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | OP_MULTIPLY |
| 2 | in | ICoreDouble | OP_DIVIDE |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Divide |
| port-count rule | PortsParam::DivideSigns |
SampleTime parameter | yes |
| always set | Multiplication = Element-wise(.*) |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 3 ports (2 in, 1 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Divide block -- element-wise product and quotient y = u1 (op) u2 (op) ... entry by entry, where each input's op is "" or "/", taken from that port's DESCRIPTION LABEL. A leading "/" is a reciprocal, exactly as in Simulink: "/" computes (1/u1)*u2. Algebraic and stateless, no state space (see header).
The three HDL backends are SIMULATION-ONLY real arithmetic, and deliberately so for the whole block rather than only for its "/" ports. A Q16.16 quotient overflows as soon as the divisor drops below |numerator| / 32768 -- one quantum of the divisor is 1.5e-5, so a perfectly ordinary signal passing near zero produces a quotient the datapath cannot hold. That is the dynamic-range argument Recursive IIR and Variable Transport Delay make, and it is the block's own name, so the cores convert at the port boundary and evaluate in
real. Doing it for every port rather than only the dividing ones keeps ONE emitted body per target: a fixed-point path taken only by an all-"*" port list is a branch the rigs never select, and an untested branch is worse than a documented limitation.
Sample results#
7 sample(s) were non-finite (nan/inf) and are absent from the plot; they are in the table below and in the JSON.
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | 1 |
| 0.4 | 0.5 | 0.5 | 1 |
| 0.8 | -2 | -2 | 1 |
| 1.2 | 0.5 | 0.5 | 1 |
| 1.6 | -2 | -2 | 1 |
| 2 | 0.5 | 0.5 | 1 |
| 2.4 | -2 | -2 | 1 |
| 2.8 | 0.5 | 0.5 | 1 |
| 3.2 | -2 | -2 | 1 |
| 3.6 | 0.5 | 0.5 | 1 |
| 4 | -2 | -2 | 1 |
| 4.4 | 0.5 | 0.5 | 1 |
| 4.8 | -2 | -2 | 1 |
| 5.2 | 0.5 | 0.5 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 1 … 1 |
ramp | Ramp: slope 1 from t = 0 | 1 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 1 … 1 |
step | Step: 0 -> 1 at t = 1 s | 1 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Divide.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).