Assignment — Control Systems/Base Blocks

Assignment

Control Systems / Base Blocks

Passes an array through, overwriting the elements you name: y = Y0, then y(index_k) = U_k for every entry of the index list. Everything not named keeps its value from Y0, so the block edits a signal in place rather than building a new one.

Ports

• Y0 – the array to modify, of any size [m,n]. It sets the output size, and every element the index list does not name passes straight through.
• U – the values to write. It must carry exactly as many elements as the index list has entries, in any shape: the k-th element of U goes to the k-th index. A single index therefore takes a scalar U.
• Output – the modified array y, always the size of Y0, whatever U's shape is.

Parameters

• Indices – which elements of Y0 to overwrite, as a vector such as [3 1]. They are linear indices read column by column – down the first column, then the second, which is how MATLAB and Simulink number the elements of an array, so for a column-vector signal the index is just the row. They need not be sorted and need not be distinct: the list is applied in the order written, so a repeated index keeps the last value assigned to it. Defaults to 1, the first element.
• Index Mode – whether the list is One-based (the first element is 1, the default and MATLAB's convention) or Zero-based (the first element is 0, C's convention). It shifts how the numbers in Indices are read; it changes nothing else.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.

The index list is structural and is resolved at export time rather than exposed as a tunable parameter: it decides which element is wired to which, and a core whose wiring could be re-pointed at run time would need a bounds check on every element on every step. The generated body is therefore a flat list of one assignment per output element, identical in shape across all ten backends. If you need the destination to move while the core runs, that is a different block.

The three HDL targets are fully synthesizable and carry no arithmetic at all – an assignment is a wire – so the fixed-point datapath is bit-identical to the reference.

Simulink bridge

Import and export, mapped to simulink/Math Operations/Assignment. "Indices" goes to Indices as a pass-through value (the two languages write a vector the same way, and both number elements column by column), "Index Mode" to IndexMode with a 1:1 One-based/Zero-based table that is therefore lossless in both directions, and "Sampling Time (s)" to SampleTime, as on every block.

Three Simulink parameters are always implied rather than chosen, and are written out as such: NumberOfDimensions 1, IndexOptions Index vector (dialog) and OutputInitialize Initialize using input port <Y0>. Those are the settings that make Simulink's block do what this one does. Taking the indices from an input port, assigning across two dimensions with a row and a column list, and initializing the output from a size table instead of a Y0 port all have no counterpart here.

Notes

• Algebraic, with no state: the output depends only on the current inputs.
• Linear – it is a selection matrix on Y0 plus a placement matrix on U – but it carries no state space, because a state space holds one input and model reduction only merges SISO blocks, so a two-input block can never be merged whatever it declares. Sum is just as linear and carries none for the same reason.
• An index outside Y0, a non-whole index, or a U whose element count does not match the list, is reported with the block's path and stops the run rather than writing past the array.