Algebraic Constraint — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Algebraic_Constraint · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Algebraic Constraint
Control Systems / Base Blocks
Searches for the signal z that makes the residual you feed back into it come out right: wire the block's output into an expression and the expression back into its input, and it moves z until f(z) = 0 (or f(z) = z, if you pick the fixed-point form). It is how you state an implicit equation in a diagram, rather than solving it by hand first.
It searches by integral action on the residual, one step per sample: dz/dt = −K·f for the zero form and dz/dt = K·(f − z) for the fixed-point form. The loop settles exactly where the residual is satisfied, and it settles there because that is the only value at which z stops moving.
Ports
- f(z) – the residual, of any size [m,n]. It is what the block drives to zero (or towards z), and the block does not care how it was computed.
- z – the trial value, the SAME size [m,n]. Every entry is solved independently, so an [m,n] residual is m×n separate constraints, not one vector equation.
Parameters
- Constraint – which relation to enforce.
- f(z) = 0 – drive the residual to zero. This is the usual form, and the default.
- f(z) = z – drive the input to equal the output, i.e. find a fixed point of whatever the loop computes.
- Initial Guess – where the search starts, as the size of the signal. A good guess reaches the answer sooner and, on a residual with more than one root, decides which root it reaches.
- Solver Gain – K, how hard the block pushes. It must be a
strictly positive scalar. Larger converges faster and, past a point, oscillates
or diverges; the loop is stable while K·df/dz is positive and not
too large, so a residual that decreases with z needs the sign put right
in the expression rather than in K. Defaults to
1. - Sampling Time (s) – the block is discrete by nature, so this is its iteration period: zero or less falls back to the model's global sampling time, and a positive value runs one relaxation step every that many seconds.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.
The exported core carries the discretization of the relaxation for the model's discretization method, and the initial guess as the seed of its persistent state, so a generated core searches exactly as the simulation did. That also means Solver Gain and Initial Guess are baked in at export time rather than exposed as tunable parameters: the gain has already been folded into the discretized coefficients, and re-tuning it on the deployed core would mean re-deriving the discretization there.
The three HDL targets carry the state in Q16.16 fixed point and are fully synthesizable. The quantum, about 1.5×10-5, is the floor on how finely the fixed-point core can resolve a root; the seven software targets resolve it to double precision. All three round each step to the nearest quantum rather than truncating it, which matters here more than it does in most blocks: in the f(z) = 0 form the search is a pure accumulation, so it never forgets a rounding bias, and a core that truncated would creep away from the root by roughly half a quantum per step for as long as it ran.
Simulink bridge
Neither direction. Simulink's
simulink/Math Operations/Algebraic Constraint is not the same mechanism:
it hands the loop to a nonlinear algebraic solver that re-evaluates f(z)
several times within one time step and returns a z satisfying the
constraint to a tolerance before the step ends. An ICore feedback loop advances
once per sample by construction – there is nothing that could re-enter the
loop mid-step – so this block converges across samples instead. The
two agree on where they settle and disagree on every step before that, which
makes them the same intent and not the same block, so the bridge reports it
rather than translating it. Simulink's Solver and
Tolerance parameters describe that in-step solver and have no
counterpart; Solver Gain is this block's own and describes the
relaxation. Note that Simulink's block, like this one, has no
SampleTime parameter.
Notes
- Stateful: one state per entry of the signal, the current trial value, seeded with the Initial Guess.
- Discrete by nature – one relaxation step per sample – so the block runs the same recursion whatever solver the model uses, and the exported core matches the simulation step for step rather than to a tolerance.
- Linear in the residual, so the block carries a continuous state space and model reduction can use it. That describes the relaxation, which is the block's actual dynamics; it says nothing about the loop the block is wired into, which is as nonlinear as the expression you wrote.
- Feedback loops in ICore carry one sample of delay per loop. That is what makes this block an iteration rather than a solve, and it is also why a loop containing it should be certified by code-export verification rather than compared step by step against Simulink.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Algebraic_Constraint |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Algebraic_Constraint |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Algebraic_Constraint/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Algebraic_Constraint.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Algebraic_Constraint/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Algebraic_Constraint.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | f(z) |
| 2 | out | ICoreDouble | z |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Constraint | f(z) = 0%~%f(z) = z~~f(z) = 0 | — |
Initial Guess | 0 | — |
Solver Gain | 1 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Algebraic Constraint hands the loop to a nonlinear solver that re-evaluates f(z) several times WITHIN one time step and returns a z satisfying the constraint before the step ends. An ICore feedback loop advances once per sample by construction, so this block relaxes towards the same answer ACROSS samples instead: the two settle in the same place and differ on every step before that. Its Solver and Tolerance parameters describe that in-step solver and have nothing to map to.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Algebraic Constraint block -- drive a residual to zero by relaxation Output z, input f(z). Wired into a loop, the block moves z until the residual on its input settles at the value the constraint asks for. It does that by INTEGRAL ACTION on the residual, one step per sample:
f(z) = 0 -> dz/dt = -K*f (A = [0], B = [-K], C = [1], D = [0]) f(z) = z -> dz/dt = K*(f - z) (A = [-K], B = [ K], C = [1], D = [0])
Both forms are LINEAR in the residual, so the block carries a real continuous state space -- seeded in the constructor from the defaults, re-derived on every loadBlockConfig -- applied independently to every entry of the signal, exactly as the Integrator applies its scalar 1/s.
setDiscreteOnlyBlock(true): the relaxation is an ITERATION, and an iteration advances per sample. There is no physical state being integrated here, and a constraint solver that converged one way in the simulation and another in the exported core would be worse than no block at all -- so the live run and all ten exports realize the identical recursion, derived from the state space above through the MODEL's discretization method (the same mechanism Integrator uses, so the choice of method is still honoured).
discretize() is called from loadBlockConfig and from the codegen helper, and NOT per step: ICoreModelBuild only discretizes the model when the solver type is discrete, and this block runs its discrete path whatever the surrounding solver is -- but discretize() also logs, so a per-step call would be one log line per step.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.1 … 0 |
ramp | Ramp: slope 1 from t = 0 | -16.53 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.9987 … 0.002431 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2.1 … 0.35 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Algebraic_Constraint.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).