Abs — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Abs · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Abs
Control Systems / Base Blocks
Outputs the absolute value of its input: y = |u|, applied entry by entry, so a matrix signal is folded element for element. Everything below zero is reflected about it; everything at or above zero passes through unchanged.
Ports
- Input – the signal u, of any size [m,n].
- Output – the folded signal y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to tune, so nothing is exposed as a parameter on the generated core.
The seven software targets use their own absolute-value built-in, which is exact on IEEE doubles everywhere. The three HDL targets carry the signal in Q16.16 fixed point and branch on the sign instead: negating a two's complement value is exact, so the fixed-point core is bit-identical to the reference and is fully synthesizable.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Abs. The block
has no parameters of its own, so the only pair is the global one:
"Sampling Time (s)" to SampleTime, as on every block. Simulink's
zero-crossing detection is a solver setting rather than a block behaviour and
does not cross.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear – |a + b| is not |a| + |b| – so the block deliberately carries no state space, and model reduction reports it as unmergeable rather than absorbing the fold into a neighbouring plant.
- Zero maps to zero, and the negative-zero case follows the target's own built-in: |−0| is +0 in every one of the ten.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Abs |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Abs |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Abs/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Abs.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Abs/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Abs.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Abs |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Abs block -- absolute value y = |u|, entry by entry. Algebraic and stateless, no state space (see header).
Every target has a built-in for this, and all of them agree on IEEE doubles, so there is no per-language convention to reconcile the way Quantizer's rounding needs one. The three HDL backends have no built-in and no need of one: negating a two's complement Q16.16 value is exact, so they branch on the sign and subtract from zero.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | 2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | 2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | 2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | 2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | 2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | 2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Abs.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).