Generated reference › FIR Identification — System Identification/Offline
kind: generated#block#system-identification-offline

FIR Identification — System Identification/Offline

System_Identification/Offline/FIR_Identification · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

FIR Identification (offline)

System Identification / Offline

Fits the least-squares impulse response of a measured input/output pair: y[k] ≈ Σi bi·u[k−i] over Filter Length taps. The block buffers both signals for the whole run and performs the fit once the run ends.

This is the robust first look that precedes any parametric fit. The model is linear in its parameters, so there is no iteration to converge and no denominator to go unstable – the solve has a single minimum and either succeeds or reports why. Use it to see the shape and length of a plant's response before choosing an order for IIR Identification or a structure for the recursive estimators.

Ports

  • u – the excitation, a [1,1] scalar per step. A PRBS Generator or Multisine Generator is the usual source.
  • y – the measured response, a [1,1] scalar per step, sampled at the same rate as u.
  • b – the fitted taps, a [N,1] column where N is Filter Length. ⚠ It holds zeros for the whole run – see Notes.

Parameters

  • Filter LengthN, the number of taps to fit, at least 1. Choose it to cover the plant's settling time in samples: too short truncates the response and biases every remaining tap, too long fits noise into the tail. The run must supply at least N samples, and comfortably more than N for the fit to mean anything.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one of them emits what the block actually does each step: a zero coefficient vector on the output port.

The fit itself is deliberately not ported. A deployable core is a per-step scan with no end-of-run hook to run a batch solve in, and the three fixed-point HDL targets could not carry a normal-equations solve meaningfully. When the identified coefficients have to exist in generated code, export Recursive Least Squares instead – its update is per-step by construction.

Simulink bridge

None. Simulink's identification blocks belong to the System Identification Toolbox, which is not installed here, so a mapping could not be parity-verified even if it were written. The bridge reports the block rather than dropping it silently, and it has no parity testbench, which is the documented consequence of Support::None rather than a gap. Code export verification still covers it across all ten languages.

Notes

  • The output port carries zeros for the entire run, by design. The fit completes at the end of the run, after the last step, so there is no step at which a meaningful coefficient could be placed on a port. The run log is the result surface – the fitted taps and the residual are written there when the run finishes. The offline IIR Identification block publishes exactly the same contract, deliberately, so the two agree on what a not-yet-fitted output means.
  • Stateful and inherently discrete: samples are collected per step, so the block declares setDiscreteOnlyBlock(true).
  • The fit is a single symmetric positive-definite solve of the normal equations. It is reported as failed, with the reason, if the run supplied fewer than N samples, or if the conditioning of those equations says the excitation cannot determine N taps – a constant input, for instance, cannot identify more than one of them. That second check is explicit rather than inherited: a least-squares solver returns a solution for a singular system without complaining, so an unchecked fit would report meaningless taps as though they had been measured.

Code facts#

FactValue
registered typeSystem_Identification/Offline/FIR_Identification
familySystem_Identification/Offline
solver environment classICoreBlock_0_System_Identification_1_Offline_2_FIR_Identification
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/System_Identification/Offline/FIR_Identification/ICoreBlock_0_System_Identification_1_Offline_2_FIR_Identification.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/System_Identification/Offline/FIR_Identification/ICoreBlock_0_System_Identification_1_Offline_2_FIR_Identification.h
default size on canvas95 × 70 px
ports at insert2 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDouble
2inICoreDouble
3outICoreDouble

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Filter Length8

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): Simulink's identification blocks belong to the System Identification Toolbox, which is not installed on this machine, so the mapping could not be parity-verified even if it were written. Fit the same data on the Simulink side with impulseest

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

FIR Identification (offline) — the least-squares impulse response of a measured (u, y) pair y[k] ~ SUM_{i=0..N-1} b_i * u[k-i]

Buffers the run, fits once at onSolverFinish(), logs the taps. The output port holds zeros throughout, which is the same contract Offline/IIR_Identification publishes -- see the header for why that is the block's real behaviour rather than a stub, and for why this block forms its own normal equations instead of calling ICoreSystemIdentification.

Sample results#

FIR Identification — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sampleFIR Identification — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample-202012345t (s)in ICoreDouble-Out-0in ICoreDouble-Out-0out ICoreDouble-Out-0 [8x1] entry 0
tin ICoreDouble-Out-0in ICoreDouble-Out-0out ICoreDouble-Out-0 [8x1] entry 0
0-2-2[0, 0, 0, 0]…
0.40.50.5[0, 0, 0, 0]…
0.8-2-2[0, 0, 0, 0]…
1.20.50.5[0, 0, 0, 0]…
1.6-2-2[0, 0, 0, 0]…
20.50.5[0, 0, 0, 0]…
2.4-2-2[0, 0, 0, 0]…
2.80.50.5[0, 0, 0, 0]…
3.2-2-2[0, 0, 0, 0]…
3.60.50.5[0, 0, 0, 0]…
4-2-2[0, 0, 0, 0]…
4.40.50.5[0, 0, 0, 0]…
4.8-2-2[0, 0, 0, 0]…
5.20.50.5[0, 0, 0, 0]…

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0 … 0
rampRamp: slope 1 from t = 00 … 0
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias0 … 0
stepStep: 0 -> 1 at t = 1 s0 … 0

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/System_Identification__Offline__FIR_Identification.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).