Hammerstein Wiener Model — System Identification/Models
System_Identification/Models/Hammerstein_Wiener_Model · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Hammerstein-Wiener Model
System Identification / Models
Simulates a single-input single-output Hammerstein-Wiener model: a static input nonlinearity, a linear block and a static output nonlinearity in series,
x = f(u), w = [B(q)/F(q)]·x, y = h(w),
where B and F are polynomials in the delay operator q−1, so w[k] = B0x[k] + B1x[k−1] + … − F1w[k−1] − …, from zero history. It is System Identification Toolbox's idnlhw model and the Simulink Hammerstein-Wiener Model block, for the nonlinearities that can be written down in numbers.
Ports
- u – the input, a scalar.
- y – the output, a scalar.
Parameters
- Input Nonlinearity – f: Unit Gain, Saturation, Dead Zone, Piecewise Linear or Polynomial.
- Input Nonlinearity Parameters – f's numbers: [lower upper] for Saturation (the linear interval; outside it the output holds the bound) and Dead Zone (the zero interval; outside it the output is the distance past the bound), where -Inf or Inf leaves that side open; a 2×K matrix [x; y] of breakpoints for Piecewise Linear, x strictly increasing, 2 to 32 of them, held FLAT beyond the first and last as idnlhw does; the coefficients highest power first for Polynomial. Ignored by Unit Gain.
- B – the linear block's numerator, a row, with the input delay as leading zeros: 1 to 20 entries.
- F – the denominator, a row starting with 1.
- Output Nonlinearity – h, from the same five.
- Output Nonlinearity Parameters – h's numbers, as for f.
- Sampling Time (s) – the model's sample time; zero or less inherits the solver's rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each prints the same description of the step that the simulation itself runs, so every target does the same arithmetic in the same order; the nonlinearities and the polynomials are baked in as constants.
⚠ The three HDL targets run in simulation-only real arithmetic, quantizing only at the port boundaries.
Simulink bridge
None (Support::None). Simulink's block takes an
idnlhw object from the workspace, which a model file does not carry;
the bridge reports this block rather than dropping it silently. Code export
verification still covers it across all ten languages.
Notes
- Discrete only, and stateful: the linear block's past values persist.
- ⚠ To copy a model from MATLAB, take B from
m.LinearModel.B: idnlhw keeps its linear block in a canonical form whose first nonzero B coefficient is 1, putting the gain into the nonlinearities. - Only single-input single-output models, and only the five nonlinearities above: sigmoid and wavelet networks, custom networks and input/output normalization are not offered.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Models/Hammerstein_Wiener_Model |
| family | System_Identification/Models |
| solver environment class | ICoreBlock_0_System_Identification_1_Models_2_Hammerstein_Wiener_Model |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Models/Hammerstein_Wiener_Model/ICoreBlock_0_System_Identification_1_Models_2_Hammerstein_Wiener_Model.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Models/Hammerstein_Wiener_Model/ICoreBlock_0_System_Identification_1_Models_2_Hammerstein_Wiener_Model.h |
| default size on canvas | 170 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Input Nonlinearity | kinds~~Piecewise Linear | — |
Input Nonlinearity Parameters | [-1 0 1; -0.8 0 0.6] | — |
B | [0 1 0.5] | — |
F | [1 -0.6] | — |
Output Nonlinearity | kinds~~Saturation | — |
Output Nonlinearity Parameters | [-1.5 1.5] | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Hammerstein-Wiener Model block takes an idnlhw object from the workspace, which a model file does not carry. The block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Hammerstein-Wiener Model -- System Identification Toolbox's idnlhw, single input and output x = f(u), w = [B(q)/F(q)] x, y = h(w)
f and h are Unit Gain, Saturation, Dead Zone, Piecewise Linear (by breakpoints) or Polynomial; the arithmetic is ICoreHammersteinWienerSupport's.
⚠ MEASURED AGAINST R2026a's idnlhw
simon 60 random models (every pairing of the five, B up to 4 coefficients after a delay of up to 2, F of order up to 3, one-sided intervals): median 3.2e-16 relative, at worst 6.0e-13 where closely spaced piecewise-linear breakpoints meet idPiecewiseLinear's sum-of-units form; and the emitted Python is bit-identical to the live run on all 12000 samples.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.