While Iterator — Private/Subsystem Components

While Iterator

Control Systems / Ports And Subsystems

Makes the subsystem it sits in a While Iterator subsystem: each step, the subsystem runs again while its condition holds, up to a maximum, and what is seen outside is the last pass. Simulink’s While Iterator block (BlockType=WhileIterator). To make one, place this block in a subsystem, or insert the ready-made While Iterator Subsystem from the library’s Subsystem Templates.

Ports

• Inputs – cond, driven from inside the subsystem and tested after each pass, and, for a while loop, IC, the condition before the first pass. A do-while loop takes only cond.
• Outputs – none while Show iteration number port is Off (the default); one, the number of passes, while it is On.

Parameters

• Maximum number of iterations – 5 (default). The cap stops the loop silently; -1 is no limit; 0 runs nothing.
• While loop type – while (default) tests the IC before the first pass; do-while always runs one.
• Reset states – held (default) or reset, once per step before the first pass.
• Show iteration number port – Off (default).
• Output data type – int32 (default).

Notes

• A subsystem is iterated by one iterator block at most, and the block has to sit inside a subsystem, never at the top level. A port count or a count that disagrees with the parameters is refused before a run, by name.
• A simulation runs the subsystem’s blocks once per pass, all at the step’s time, and what is seen outside is the last pass. Inside, every block inherits its rate (-1) or is constant; a continuous block, a block with its own rate and a Discrete-Time Integrator (elapsed time) are refused by name, as R2026a refuses them.

Code export

The subsystem exports as a loop around its blocks, with the same passes as the simulation, the condition tested after each one: Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text. A Maximum number of iterations of -1 is refused by name, since exported code must finish every step. VHDL, Verilog and SystemVerilog run at most one pass per clock tick and refuse a While subsystem by name. Reset states reset is carried wherever the loop is.

Simulink bridge

Import and export, mapped to built-in/WhileIterator; the library’s While Iterator Subsystem imports with what R2026a puts in it (an In1, an IC Inport wired to the block’s IC input, the While Iterator, an Out1, In1 wired to Out1, atomic; the condition input left open). Every parameter crosses: Maximum number of iterations to MaxIters, While loop type to WhileBlockType, Reset states to ResetStates, Show iteration number port to ShowIterationPort and Output data type to OutputDataType. Its ports follow its parameters on both sides.