Variant Merge — Private/Subsystem Components
Private/Subsystem_Components/Variant_Merge · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Variant Merge
Control Systems / Ports And Subsystems
The output side of a Variant Subsystem: it passes on whichever input is wired from the subsystem’s active choice, and the other choices leave the run. Place it inside a Subsystem whose Variant is On, one per output: wire output k of every choice to it, and it to the output gate. The ready-made Variant Subsystem (Ports & Subsystems templates) holds one, with its first choice wired; add a choice by wiring its output to the merge's next input.
Ports
- u1 … uN – one per choice, from that choice’s output. The inputs need not agree in size: only the active one is read.
- Output – the active choice’s value, unchanged. When the active choice feeds none of the inputs, the output is 0.
Parameters
- None of its own. Which input it passes on follows the Variant Subsystem it sits in: that subsystem’s Variant Control Mode, Label Mode Active Choice, and each choice’s Variant Control. Its Active Choice is not read.
Code export
All ten targets, as a copy of the active choice’s output; the inactive choices are not exported at all.
Simulink bridge
Not a Simulink block. Simulink matches a Variant Subsystem’s unwired choices to its ports by name; the bridge builds this merge when it imports one and takes it out when it exports one.
Notes
- Placed anywhere but directly inside a Variant Subsystem it has no choice to follow and passes on its first input.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Variant_Merge |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Variant_Merge |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Variant_Merge/ICoreBlock_0_Private_1_Subsystem_Components_2_Variant_Merge.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Variant_Merge/ICoreBlock_0_Private_1_Subsystem_Components_2_Variant_Merge.h |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (2 in, 1 out) or from the block's configuration.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): a Variant Subsystem's output side: built and taken out by the bridge with the Variant Subsystem it belongs to, never mapped through the catalog
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.