Trigger Port — Private/Subsystem Components
Private/Subsystem_Components/Trigger_Port · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Trigger Port
Control Systems / Ports And Subsystems
Makes the subsystem it sits in a triggered subsystem: the subsystem runs only on the steps its trigger signal has an edge of the chosen kind. Simulink’s Trigger block (BlockType=TriggerPort). To make one, place this block in a subsystem, or insert the ready-made Triggered Subsystem, Enabled and Triggered Subsystem or, with Trigger type function-call, Function-Call Subsystem from the library’s Subsystem Templates.
Ports
- Face – placing it inside a subsystem adds a control input on the top edge of the subsystem block, labelled Trigger. The control signal is wired there.
- Output – one, inside the subsystem: the edge that ran it, +1 on a rising edge and −1 on a falling one, held between them, as Simulink’s Show output port gives it (measured on R2026a). On a message trigger it is the value the message carries, a plain signal, held between messages. Leaving it unconnected is fine.
Parameters
- Trigger type – rising (default), falling, either, function-call or message. An edge follows Simulink’s three-way sign rule (negative, zero, positive), not a plain threshold. function-call makes the subsystem a function-call subsystem: its face takes a function-call signal and nothing else, and the subsystem runs only when its caller calls it, at the caller's place in the step, once per call. Its states advance per call, its outputs hold between calls and read their Initial output before the first, and a Discrete-Time Integrator inside is refused (Simulink integrates the time between calls there). The port's own output is not offered on a function-call trigger: it has no edge to give, so a wired output is refused. message makes it a message-triggered subsystem: its face takes a message line and nothing else, and what the subsystem does with the messages is the Trigger time. Messages that are a bus (a Hit Crossing Probe’s) are refused with the port’s name: the port gives a matrix, so read a bus message with a Receive.
- Trigger time (message triggers only) – on message available (default, Simulink’s Message Triggered Subsystem): the subsystem runs once for every message that arrives, at its place in the step, so two messages in one step run it twice, in the order they were sent. on sample time hit (Simulink’s Message Polling Subsystem): on each of its hits it takes one message and runs once, and on a hit with no message it does not run. Its face keeps one message, the newest, as a Receive without a queue does; put a Queue in front to keep more. Either way its outputs read their Initial output until the first message, and hold between runs. These are R2026a’s numbers with Schedule as aperiodic partition off; Simulink’s default (on) is refused there under a fixed-step single-tasking solver, and messages here are delivered within the fixed step.
- States when enabling – held (default), reset or inherit.
- Initial trigger signal state – the sign assumed before the first step. The default never fires at the first step.
Notes
- A subsystem holds at most one of these. It has to sit inside a subsystem, never at the top level.
- A simulation runs the subsystem only when this port says so; while it does not run, its blocks hold their states and each output port does what its Output when disabled says.
Code export
A message trigger is a loop at the subsystem's place in the step, one pass per message waiting on its queue (at most one when it polls), each pass taking one into the port's output, in Python, MATLAB, Java, Rust, C and C++; VHDL, Verilog, SystemVerilog and PLC Structured Text refuse a message line by name. Otherwise all ten targets: the subsystem's blocks run under a guard that reads the edge, so they execute exactly on the steps it triggers them, and States when enabling reset re-seeds them. A function-call subsystem is a loop at its place in the step, one pass per call its caller made, in Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text; its outputs read their Initial output until the first call. VHDL, Verilog and SystemVerilog refuse it by name: they run at most one pass per clock tick. A caller with a sample time of its own is refused too, because the exported step calls on every step.
Simulink bridge
Both directions, as Simulink’s built-in/TriggerPort inside the
subsystem and the subsystem’s Trigger input on its face.
Trigger type, States when enabling and Initial trigger signal
state go to TriggerType, StatesWhenEnabling and
InitialTriggerSignalState, one value for one value, and
Trigger time to TriggerTime. A function-call and a message
trigger cross both ways as TriggerType function-call and
message. A message trigger is exported with
ScheduleAsAperiodic off, the setting it runs with here;
one imported with it on is reported and runs the same way. The
library’s Message Triggered Subsystem and Message Polling
Subsystem import as a subsystem holding this port, with the Trigger time each
is made with, wired to its one output. An output wired inside turns
on ShowOutputPort; both sides give the edge. The numbered inputs keep
their numbers either way.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Trigger_Port |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Trigger_Port |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Trigger_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Trigger_Port.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Trigger_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Trigger_Port.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 1 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Trigger type | rising%~%falling%~%either%~%function-call%~%message~~rising | TriggerType |
States when enabling | held%~%reset%~%inherit~~held | StatesWhenEnabling |
Initial trigger signal state | compatibility (no trigger on first evaluation)%~%zero%~%p… | InitialTriggerSignalState |
Trigger time | on message available%~%on sample time hit~~on message ava… | TriggerTime |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/TriggerPort |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Trigger type | TriggerType | rising → rising, falling → falling, either → either, function-call → function-call, message → message |
States when enabling | StatesWhenEnabling | held → held, reset → reset, inherit → inherit |
Initial trigger signal state | InitialTriggerSignalState | compatibility (no trigger on first evaluation) → compatibility (no trigger on first evaluation), zero → zero, positive → positive, negative → negative |
Trigger time | TriggerTime | on message available → on message available, on sample time hit → on sample time hit |
Caveat (shown to the user): Simulink's Trigger port block (built-in/TriggerPort) inside the subsystem it controls, and the subsystem's Trigger input on the face (FEATURES_TO_ADD.md BF2.6). A function-call trigger crosses since BF7.5, a message trigger since BF4.8 (exported with ScheduleAsAperiodic off). Its output, when wired inside, is Simulink's ShowOutputPort.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.