Subsystem — Private/Subsystem Components
Private/Subsystem_Components/Subsystem · 0 input / 0 output port(s) at insert · no code generators declared
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Subsystem
Subsystem Components
A block that contains a diagram of its own. Double-click it to open the level inside, where the subsystem is built from ordinary blocks like any other canvas.
Ports
A subsystem has no port list of its own: its ports are the gates placed inside it. Add an Input Gate inside and a matching input port appears on the block here; add an Output Gate and an output port appears. Signal sizes travel through the gates, so nothing has to be declared twice.
Code export
All ten targets, structurally. A subsystem generates no solve code of its own – it has no arithmetic to emit. What reaches Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text is the code of the blocks inside it; the exporter flattens the hierarchy and each contained block emits for the target as usual.
Simulink bridge
Handled structurally, not through the block catalog. The bridge rebuilds the hierarchy on the far side rather than mapping this block to a library primitive, which is why it carries no parameter mapping.
Notes
- Grouping is structural, not numerical: the blocks inside are solved as part of the same model, and nesting one level changes no result.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Subsystem |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Subsystem |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Subsystem/ICoreBlock_0_Private_1_Subsystem_Components_2_Subsystem.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Subsystem/ICoreBlock_0_Private_1_Subsystem_Components_2_Subsystem.h |
| default size on canvas | 160 × 120 px |
| ports at insert | 0 in, 0 out |
| code generators implemented | none |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): handled structurally by the bridge, not via the catalog
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.