Reset Port — Private/Subsystem Components
Private/Subsystem_Components/Reset_Port · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Reset Port
Control Systems / Ports And Subsystems
Makes the subsystem it sits in a resettable subsystem: on each step its reset signal fires, every state inside returns to its initial condition before that step’s outputs, and the step then runs. Simulink’s Reset block (BlockType=ResetPort). To make one, place this block in a subsystem, or insert the ready-made Resettable Subsystem from the library’s Subsystem Templates.
Ports
- Face – placing it inside a subsystem adds a control input on the top edge of the subsystem block, labelled Reset. The control signal is wired there.
- Output – one, inside the subsystem: the control signal itself. Leaving it unconnected is fine. Simulink’s Reset block has no output at all (it has no Show output port; measured on R2026a).
Parameters
- Reset trigger type – rising (default), falling, either, level (also resets on the step the signal returns to zero) or level hold (does not).
Notes
- A subsystem holds at most one of these. It has to sit inside a subsystem, never at the top level.
- Alone, it never stops the subsystem running: the subsystem runs on every step, as R2026a’s Resettable Subsystem does, and on a step its reset fires the states are re-seeded first. Beside an Enable or Trigger port, a reset is applied only on a step the subsystem runs.
Code export
All ten targets: on a step its reset fires (an edge, by the same sign rule as a trigger, or a level), every state inside is re-seeded before that step's outputs, and the step then runs. On VHDL, Verilog, SystemVerilog and PLC-ST a state the re-seed cannot copy back is refused by name. Also refused by name: a reset driven by a String or bus signal, a resettable subsystem inside an iterated one, and one inside, or holding, a reusable function on every target but Verilog and SystemVerilog.
Simulink bridge
Both directions, as Simulink’s built-in/ResetPort inside the
subsystem and the subsystem’s Reset input on its face.
Reset trigger type goes to ResetTriggerType, one value for one
value. A wire from this block’s output does not cross, and the export says
so, because Simulink’s Reset block has none. The numbered inputs keep their
numbers either way.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Reset_Port |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Reset_Port |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Reset_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Reset_Port.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Reset_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Reset_Port.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 1 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Reset trigger type | rising%~%falling%~%either%~%level%~%level hold~~rising | ResetTriggerType |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/ResetPort |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Reset trigger type | ResetTriggerType | rising → rising, falling → falling, either → either, level → level, level hold → level hold |
Caveat (shown to the user): Simulink's Reset port block (built-in/ResetPort) inside the subsystem it controls, and the subsystem's Reset input on the face (FEATURES_TO_ADD.md BF2.6). Simulink's Reset port has no output, so a wire from ICore's inside the subsystem does not cross.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.