Function Call Generator — Private/Subsystem Components
Private/Subsystem_Components/Function_Call_Generator · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Function-Call Generator
Control Systems / Ports And Subsystems
Calls a function-call subsystem: on each of its sample hits it runs the
subsystem its line reaches, Number of iterations times, at its own place in
the step. Simulink’s Function-Call Generator
(BlockType=FunctionCallGenerator). The subsystem it calls holds a Trigger Port of Trigger type function-call; the library’s Subsystem Templates hold a ready-made Function-Call Subsystem.
Ports
- Output – a function call (badge
fcn), not data: wire it to a subsystem whose Trigger port has Trigger type function-call. A sink or any data input refuses it, and one call line calls one subsystem. It has no inputs.
Parameters
- Number of iterations – how many times each hit calls, a positive integer (default 1). A row vector gives one call line per element, called that many times each; a Demux splits them. Zero, a negative or a non-integer is refused before a run, as Simulink refuses it.
- Sampling Time (s) – how often it calls; zero or less inherits the solver’s rate. A period of its own takes effect under a fixed-step Continuous solver, which runs blocks at their own rates; the Discrete solver runs every block every step.
Code export
Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text: the call line carries the count, and the called subsystem runs as a loop of that many passes at its place in the step. VHDL, Verilog and SystemVerilog refuse a function call by name: they run at most one pass per clock tick. A Sampling Time of its own is refused in every target, because the exported step calls on every step.
Simulink bridge
Import and export, as built-in/FunctionCallGenerator:
Number of iterations to NumberOfIterations and the rate to
SampleTime. Its enable port (ShowEnablePort) is not
offered.
Notes
- A called subsystem’s states advance once per call, so 2 iterations per step advance a counter inside by 2 each step.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Function_Call_Generator |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Generator |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Function_Call_Generator/ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Generator.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Function_Call_Generator/ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Generator.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreFunctionCall | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Number of iterations | 1 | NumberOfIterations |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/FunctionCallGenerator |
| port-count rule | PortsParam:: |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Number of iterations | NumberOfIterations | passes through |
Caveat (shown to the user): Simulink's Function-Call Generator (FEATURES_TO_ADD.md BF7.5): NumberOfIterations and
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Function-Call Generator -- calls what it is wired to, NumberOfIterations times per hit Simulink's Function-Call Generator (BlockType=FunctionCallGenerator, FEATURES_TO_ADD.md BF7.1 measured it): its one output is a FUNCTION CALL (ICoreFunctionCall), not data, and each sample hit it calls the function-call subsystem its line reaches as many times as its Number of iterations says. A vector gives a wide call line, one count per element (a Demux then splits it). Live, the count it writes is what ICoreSubsystemActivity::dispatchCalls reads after this block solves (BF7.3); exported, it is the count a called subsystem's loop reads at its face (BF7.4).
The value is a held matrix, so the solver and the code export are Constant's, copied: the block writes its Number of iterations onto its port every step. Built inside FEATURES_TO_ADD.md BF7.5 so a function-call diagram has a source that crosses to Simulink; its library row is BF7.6's.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.