Function Call Feedback Latch — Private/Subsystem Components
Private/Subsystem_Components/Function_Call_Feedback_Latch · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Function-Call Feedback Latch
Control Systems / Ports And Subsystems
Carries a function-call subsystem’s own output back to one of its
data inputs: y = u as its PREVIOUS call left it. Without it, a data input
that depends on a block inside the subsystem’s own calling context is
refused, as Simulink refuses it (FcnCallSSSrcInsideContext).
Simulink’s Function-Call Feedback Latch
(BlockType=FunctionCallFeedbackLatch).
Ports
- Input – u, a value produced inside the calling context of the subsystem the output feeds: that subsystem’s output, or one from a subsystem called with it. Any size.
- Output – y, the size of u. It must be wired to exactly one data input of a function-call subsystem.
Parameters
- Sampling Time (s) – zero or less inherits the solver’s rate; a positive value runs the block at that period. Simulink’s block has none: it runs at its caller’s rate, and so does the copy each call makes here.
Code export
Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text: a copy of u onto y at the block’s place, and again at the head of each call of the subsystem it feeds, so a second call in one step reads what the first left. VHDL, Verilog and SystemVerilog emit the same copy, but they refuse the function-call subsystem around it by name (one pass per clock tick), so no hardware export holds one.
Simulink bridge
Both directions, as simulink/Ports & Subsystems/Function-Call
Feedback Latch. It has no dialog parameters and no
SampleTime, so nothing else crosses.
Notes
- It runs as R2026a measured: with one call a step a subsystem reads the value its previous call produced, which is what a Unit Delay would give in Simulink; with two or more calls a step each call reads the one before it in the same step, which a Unit Delay does not.
- Refused before a run, in Simulink’s words: an output that is not
wired to exactly one data input of a function-call subsystem
(
CannotLogFuncCallLatch), an input that does not come from a function-call subsystem (FcnCallLatchNoFeedbackSignal3), and an input from a subsystem called by another initiator than the one it feeds (FcnCallLatchNoFeedbackSignal2).
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Function_Call_Feedback_Latch |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Feedback_Latch |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Function_Call_Feedback_Latch/ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Feedback_Latch.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Function_Call_Feedback_Latch/ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Feedback_Latch.h |
| default size on canvas | 70 × 60 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Ports & Subsystems/Function-Call Feedback Latch |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): Simulink's Function-Call Feedback Latch has no dialog parameters and no SampleTime.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Function-Call Feedback Latch -- a called subsystem's output back to its own input Simulink's Function-Call Feedback Latch (BlockType=FunctionCallFeedbackLatch): no dialog parameters, one data input, one data output. R2026a refuses a function-call subsystem whose data input depends on a block inside its own calling context (FcnCallSSSrcInsideContext) unless the path goes through this block, and then hands the subsystem what its PREVIOUS call left on that path. Measured on R2026a (A{u+1 -> B{10u}}, B's output latched into A's input): one call a step gives a = [1 11 111 1111], as a Unit Delay would; two calls a step give [11 1111 ...], the second call reading the first's value, which a Unit Delay does not.
Here it is a pass-through with no direct feedthrough, so the build opens the loop at it and places it after the subsystem it reads; the call driver (ICoreModelSimulator) and code export (ICoreConditionalExport) copy its input onto its output again before each call of the subsystem it feeds. Where it comes from: BLOCKS_TO_ADD_SIMULINK_FAMILIES.md, Family E, on FEATURES_TO_ADD.md BF7 and BF7.7 (the caller ordering it needs).
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.