Enable Port — Private/Subsystem Components
Private/Subsystem_Components/Enable_Port · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Enable Port
Control Systems / Ports And Subsystems
Makes the subsystem it sits in an enabled subsystem: the subsystem runs only on the steps its enable signal is strictly greater than zero. Simulink’s Enable block (BlockType=EnablePort). To make one, place this block in a subsystem, or insert the ready-made Enabled Subsystem or Enabled and Triggered Subsystem from the library’s Subsystem Templates.
Ports
- Face – placing it inside a subsystem adds a control input on the top edge of the subsystem block, labelled Enable. The control signal is wired there.
- Output – one, inside the subsystem: the control signal itself, as Simulink’s Show output port gives it. Leaving it unconnected is fine.
Parameters
- States when enabling – held (default) keeps every state across a disabled span; reset returns them to their initial conditions on the step the subsystem is enabled again.
Notes
- A subsystem holds at most one of these. It has to sit inside a subsystem, never at the top level.
- A simulation runs the subsystem only when this port says so; while it does not run, its blocks hold their states and each output port does what its Output when disabled says.
Code export
All ten targets: the subsystem's blocks run under a guard that reads the enable signal, so they execute exactly on the steps it is above zero (any element, for a vector), and each output port holds or resets as its Output when disabled says. States when enabling reset re-seeds the states on the first step the subsystem runs again; on VHDL, Verilog, SystemVerilog and PLC-ST a state the re-seed cannot copy back is refused by name. Also refused by name: an enable driven by a String or bus signal, an enabled subsystem inside an iterated one, and one inside, or holding, a reusable function on every target but Verilog and SystemVerilog.
Simulink bridge
Both directions, as Simulink’s built-in/EnablePort inside the
subsystem and the subsystem’s Enable input on its face.
States when enabling goes to StatesWhenEnabling, one value for
one value. An output wired inside turns on ShowOutputPort, which
gives the same signal. The numbered inputs keep their numbers either way.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Enable_Port |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Enable_Port |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Enable_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Enable_Port.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Enable_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Enable_Port.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 1 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
States when enabling | held%~%reset~~held | StatesWhenEnabling |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/EnablePort |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
States when enabling | StatesWhenEnabling | held → held, reset → reset |
Caveat (shown to the user): Simulink's Enable port block (built-in/EnablePort) inside the subsystem it controls, and the subsystem's Enable input on the face (FEATURES_TO_ADD.md BF2.6). Its output, when wired inside, is Simulink's ShowOutputPort.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.