One Hot Encoder — Machine Learning/Preprocessing
Machine_Learning/Preprocessing/One_Hot_Encoder · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
One Hot Encoder
Machine Learning / Preprocessing
Turns a class index into an indicator column: the selected element is 1, every other element is 0.
The categorical front end of any model whose inputs are not all continuous – a mode selector, a gear, a fault code – and the exact inverse of Argmax Decision. The index arrives as an ordinary signal and is rounded to the nearest whole number, so a value of 2.0 and one of 1.9997 select the same class.
Ports
- k – the class index, a scalar [1,1]. Interpreted relative to Index Base.
- Output – y, a column [K,1] where K is Number Of Classes. Exactly one element is 1 whenever the index is in range.
Parameters
- Number Of Classes – K, the output height; a whole number ≥ 1. Rounded to the nearest whole number if you give it a fraction.
- Index Base – what the first class is called:
- Zero-based (PyTorch, numpy) – index 0 selects the first element. The default.
- One-based (MATLAB) – index 1 selects the first element.
- Out Of Range – what an index outside the K classes does:
- All Zeros – the output is entirely zero, which is sklearn's
handle_unknown='ignore'. The default, and the one that lets a downstream block notice that nothing was selected. - Clamp To Range – below the first class selects the first, above the last selects the last. Choose this only when every out-of-range value genuinely belongs to the nearest class.
- All Zeros – the output is entirely zero, which is sklearn's
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. K, the base and the out-of-range rule are all structural and baked in; there is no tunable parameter.
No backend converts the index to an integer. Each element is emitted
as a half-open comparison – (k − base) − i in
−0.5, +0.5) – which is the same function as
floor(x + 0.5) == i without needing an integer type. Every integer
cast in these ten languages truncates toward zero, which would send a negative
index to class 0 instead of out of range.
The three HDL targets are ordinary Q16.16 fixed point and are offered for synthesis: one subtraction and a comparison per class.
Simulink bridge
None. Simulink has no one-hot block:
Multiport Switch routes signals by an index rather than producing
an indicator, and the Deep Learning blocks take a trained network
object. The bridge reports the block rather than dropping it silently, and
it has no parity testbench, which is the documented consequence of
Support::None rather than a gap.
Notes
- Algebraic and stateless: the output depends only on the current input, so the block cannot break an algebraic loop.
- Nonlinear and discontinuous, and deliberately carries no state space.
- The rounding boundary is a discontinuity, and the HDL targets sit one quantum away from the reference. They compare Q16.16 values (one quantum ≈ 1.5e-5) where the in-app run compares doubles, so an index within that distance of a ±0.5 boundary can round the other way and select a different class. Feed this block a genuinely integral index – which is what a category is – and the question never arises; feed it a continuous quantity and it is inherent, not a codegen defect.
Code facts#
| Fact | Value |
|---|---|
| registered type | Machine_Learning/Preprocessing/One_Hot_Encoder |
| family | Machine_Learning/Preprocessing |
| solver environment class | ICoreBlock_0_Machine_Learning_1_Preprocessing_2_One_Hot_Encoder |
| source | [src/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Preprocessing/One_Hot_Encoder/ICoreBlock_0_Machine_Learning_1_Preprocessing_2_One_Hot_Encoder.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Preprocessing/One_Hot_Encoder/ICoreBlock_0_Machine_Learning_1_Preprocessing_2_One_Hot_Encoder.h |
| default size on canvas | 120 × 84 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | k |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Number Of Classes | 4 | — |
Index Base | Zero-based (PyTorch, numpy)%~%One-based (MATLAB)~~Zero-ba… | — |
Out Of Range | All Zeros%~%Clamp To Range~~All Zeros | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): no Simulink equivalent: Multiport Switch routes SIGNALS by an index rather than producing an indicator column, and the Deep Learning blocks take a trained network OBJECT. There is no parameter set this block could map onto
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
One Hot Encoder — a class index in, a [K,1] indicator column out y[i] = 1 when (k - base) - i lies in [-0.5, +0.5) else 0
That half-open interval test IS floor(x + 0.5) == i, written without an integer conversion. See the header for why that matters: every integer cast in this list of ten languages truncates toward zero, which sends a negative index to class 0 instead of out of range, and the three HDL targets would need fx_to_int on top. One rule, ten identical spellings.
The three HDL targets are genuine Q16.16 -- comparisons and constants only, no arithmetic beyond one subtraction.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [4x1] entry 0 |
|---|---|---|
| 0 | -2 | [0, 0, 0, 0] |
| 0.4 | 0.5 | [0, 1, 0, 0] |
| 0.8 | -2 | [0, 0, 0, 0] |
| 1.2 | 0.5 | [0, 1, 0, 0] |
| 1.6 | -2 | [0, 0, 0, 0] |
| 2 | 0.5 | [0, 1, 0, 0] |
| 2.4 | -2 | [0, 0, 0, 0] |
| 2.8 | 0.5 | [0, 1, 0, 0] |
| 3.2 | -2 | [0, 0, 0, 0] |
| 3.6 | 0.5 | [0, 1, 0, 0] |
| 4 | -2 | [0, 0, 0, 0] |
| 4.4 | 0.5 | [0, 1, 0, 0] |
| 4.8 | -2 | [0, 0, 0, 0] |
| 5.2 | 0.5 | [0, 1, 0, 0] |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Machine_Learning__Preprocessing__One_Hot_Encoder.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).