Argmax Decision — Machine Learning/Preprocessing
Machine_Learning/Preprocessing/Argmax_Decision · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Argmax Decision
Machine Learning / Preprocessing
Reduces a column to the position of its largest entry and that entry's value:
idx = argmax(u) + base, max = uargmax(u)
This is what turns a classifier's output into a decision a controller can switch on. Put it after Softmax to get the predicted class and its probability, or straight after the final Dense Layer – softmax is monotone, so the winning index is the same either way, and only the value beside it changes meaning (a logit rather than a probability).
Ties go to the lowest index. The scan replaces its running best only on a strictly greater value, which is numpy's and PyTorch's rule.
Ports
- u – the scores, a column [m,1] with m ≥ 1 – logits, probabilities or any comparable quantity.
- idx – a scalar [1,1]: the winning position, plus Index Base. It is carried as a real number like every other signal in the model; it is always a whole one.
- max – a scalar [1,1]: the winning entry's value, in whatever units u carried.
Parameters
- Index Base – what the first element is called:
- Zero-based (PyTorch, numpy) – the first class is 0. The default, and what a model exported from a Python framework expects.
- One-based (MATLAB) – the first class is 1, for a graph whose downstream lookup or switch is written in MATLAB's convention.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The index base is baked into the body at export time; there is no tunable parameter.
The three HDL targets are genuine Q16.16 fixed point here – the block only compares and copies, with no transcendental in it – but see the Notes on what that costs at a near-tie.
Simulink bridge
None. Simulink's MinMax returns the extreme value
and has no index output, and its Compare To Constant family answers
a different question, so there is no block whose parameters this one could map
onto. The bridge reports it rather than dropping it silently, and it has no
parity testbench, which is the documented consequence of
Support::None rather than a gap. Code export verification still
covers it across all ten languages.
Notes
- Algebraic and stateless: the outputs depend only on the current input, so the block cannot break an algebraic loop.
- Nonlinear and discontinuous, and deliberately carries no state space. The index steps rather than varies, so no A/B/C/D describes it and model reduction correctly refuses the block.
- At a near-tie the HDL targets can rank differently. They compare Q16.16 values, one quantum of which is about 1.5e-5, where the in-app run compares doubles – so two scores closer together than that can come out the other way round, and the idx output then differs by a whole index rather than by a rounding error. This is inherent to reducing a continuous quantity to a discrete decision in fixed point, not a codegen defect: if your application must agree bit for bit with the simulation at a tie, separate the scores or make the decision downstream in floating point.
Code facts#
| Fact | Value |
|---|---|
| registered type | Machine_Learning/Preprocessing/Argmax_Decision |
| family | Machine_Learning/Preprocessing |
| solver environment class | ICoreBlock_0_Machine_Learning_1_Preprocessing_2_Argmax_Decision |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Preprocessing/Argmax_Decision/ICoreBlock_0_Machine_Learning_1_Preprocessing_2_Argmax_Decision.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Preprocessing/Argmax_Decision/ICoreBlock_0_Machine_Learning_1_Preprocessing_2_Argmax_Decision.h |
| default size on canvas | 120 × 80 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | idx |
| 3 | out | ICoreDouble | max |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Index Base | Zero-based (PyTorch, numpy)%~%One-based (MATLAB)~~Zero-ba… | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): no Simulink equivalent: MinMax returns the extreme VALUE and has no index output, and nothing else in the Math Operations library reports the position of a maximum, so there is no parameter set this block could map onto
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Argmax Decision — which class won, and by how much idx = argmax(u) + base max = u[argmax(u)] (ties: LOWEST index wins)
Every backend performs the identical scan: seed the running best with element 0, replace it only on a STRICTLY greater value. Nine of the ten write that as statements; the tenth (VHDL) does too, because a conditional expression is not a primary there. What none of them do is anything cleverer -- a "clever" argmax that scanned backwards, or used >=, would break the tie rule and disagree with the reference on exactly the samples that tie.
The accumulator is the OUTPUT ELEMENT itself in the three HDL bodies and in PLC ST, which is legal in all four because those are process VARIABLES (VHDL
:=, Verilog/SV blocking=, ST:=) and read back what was just written. That is the one place where §4's "registered-write rule" needs checking rather than assuming, and it does not apply: none of these is a state signal carried across a clock edge, they are all within one tick.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 | out ICoreDouble-Out-1 |
|---|---|---|---|
| 0 | -2 | 0 | -2 |
| 0.4 | 0.5 | 0 | 0.5 |
| 0.8 | -2 | 0 | -2 |
| 1.2 | 0.5 | 0 | 0.5 |
| 1.6 | -2 | 0 | -2 |
| 2 | 0.5 | 0 | 0.5 |
| 2.4 | -2 | 0 | -2 |
| 2.8 | 0.5 | 0 | 0.5 |
| 3.2 | -2 | 0 | -2 |
| 3.6 | 0.5 | 0 | 0.5 |
| 4 | -2 | 0 | -2 |
| 4.4 | 0.5 | 0 | 0.5 |
| 4.8 | -2 | 0 | -2 |
| 5.2 | 0.5 | 0 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Machine_Learning__Preprocessing__Argmax_Decision.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).