Generated reference › Debounced Decision — Machine Learning/Postprocessing
kind: generated#block#machine-learning-postprocessing

Debounced Decision — Machine Learning/Postprocessing

Machine_Learning/Postprocessing/Debounced_Decision · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Debounced Decision

Machine Learning / Postprocessing

Holds the class it is currently reporting until N consecutive samples agree on a different one. The index passes through unchanged in value – what changes is when it is allowed to move.

This is what stops a classifier chattering a controller between modes on a single noisy sample. Put it after Argmax Decision, whose index it takes and whose index it returns.

A lone disagreeing sample cannot move the output at all, and it throws away whatever evidence had been collected. That is the LATCH behaviour; if you want a lone sample to be outvoted rather than to reset the count, use Temporal Majority Vote, which is the same decision-stabiliser in its smoothing form.

Ports

  • k – the raw class index, a scalar [1,1], as Argmax Decision reports it. Class i is the one whose window [i−0.5, i+0.5) the index falls in, after Index Base has been subtracted.
  • cls – a scalar [1,1]: the class being held, reported in the same base as the input.
  • count – a scalar [1,1]: how many consecutive samples have now agreed on the pending candidate. It is 0 whenever the input agrees with the class already held, and it returns to 0 on the sample that switches. Watch it to see a switch coming.

Parameters

  • Number Of Classes – K, a whole number ≥ 1. The classes are the K windows starting at the index base; anything outside them is not a class.
  • Index Base – what the first class is called:
    • Zero-based (PyTorch, numpy) – the first class is 0. The default.
    • One-based (MATLAB) – the first class is 1.
    It shifts both the input window and the reported index by the same amount, so a graph that is consistent about the base cannot notice it.
  • Confirmations – N, a whole number ≥ 1: how many consecutive samples must agree on a new class before the output moves. At N = 1 the block is a pass-through (every valid sample switches immediately), which is the documented degenerate case rather than a misconfiguration.
  • Initial Class – the class position held before any evidence arrives, counted from 0 whatever the base. It must be less than K.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. K, the base, N and the initial class are baked into the body at export time; there is no tunable parameter, because every one of them changes which comparisons are emitted rather than merely what they compare against.

The three HDL targets are genuine synthesizable Q16.16, not the simulation-only real path: the whole block is comparisons, constant assignments and one increment, with no division and no transcendental. The class windows are compared in fixed point directly, so nothing converts through an integer type.

Simulink bridge

None. Simulink has no decision debouncer: Detect Change reports that a signal has moved, and the Discrete library's delays and counters would have to be assembled into this behaviour rather than mapping onto it, so there is no parameter set this block could cross through. The bridge reports it rather than dropping it silently, and it has no parity testbench, which is the documented consequence of Support::None rather than a gap. Code export verification still covers it across all ten languages.

Notes

  • Stateful, and inherently discrete – the run counter advances once per sample, so the block declares setDiscreteOnlyBlock and takes its rate from its own Sampling Time (s). It carries no state space and model reduction correctly refuses it: the output steps rather than varies.
  • An index outside every class window is not evidence. It leaves the held class, the pending candidate and the count exactly as they were. A dropout or an unmapped category therefore cannot discard evidence already collected, and cannot contribute any.
  • The switch takes effect on the confirming sample – the Nth agreeing sample already reports the new class, rather than the one after it.
  • At a window boundary the HDL targets can decide differently. They compare Q16.16 values, one quantum of which is about 1.5e-5, where the in-app run compares doubles – so an index within that distance of a ±0.5 boundary can fall in the neighbouring class, and the decision then differs by a whole class rather than by a rounding error. This is inherent to reducing a continuous quantity to a discrete class in fixed point, and it is the same caveat Argmax Decision and Embedding Lookup carry. Feed this block a genuinely integral index – which is what Argmax Decision produces – and no sample is ever near a boundary.

Code facts#

FactValue
registered typeMachine_Learning/Postprocessing/Debounced_Decision
familyMachine_Learning/Postprocessing
solver environment classICoreBlock_0_Machine_Learning_1_Postprocessing_2_Debounced_Decision
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Postprocessing/Debounced_Decision/ICoreBlock_0_Machine_Learning_1_Postprocessing_2_Debounced_Decision.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Postprocessing/Debounced_Decision/ICoreBlock_0_Machine_Learning_1_Postprocessing_2_Debounced_Decision.h
default size on canvas140 × 80 px
ports at insert1 in, 2 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoublek
2outICoreDoublecls
3outICoreDoublecount

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Number Of Classes4
Index BaseZero-based (PyTorch, numpy)%~%One-based (MATLAB)~~Zero-ba…
Confirmations2
Initial Class0

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): no Simulink equivalent: Detect Change reports that a signal has moved and the Discrete library's delays and counters would have to be ASSEMBLED into this behaviour rather than mapping onto it, so there is no single block whose parameters this one could cross through, and nothing to run a parity testbench against

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Debounced Decision — hold the class until N consecutive samples agree on a different one Class i is observed when (k - base) - i lies in [-0.5, +0.5) -- One_Hot_Encoder's rule verbatim, so no integer conversion appears in any of the ten backends and the three HDL targets stay in Q16.16.

The latch, in the order every backend spells it:

obs == held -> the run is thrown away (run = 0) obs == cand, run > 0 -> the run grows (run = run + 1) obs is anything else -> a NEW candidate starts (cand = obs, run = 1) run reaches N -> the switch happens NOW (held = cand, run = 0) obs is no class at all -> nothing moves (a dropout is not evidence)

The one ordering decision worth stating: the switch is applied BEFORE the output is published, so the Nth agreeing sample is already reporting the new class. The alternative (publish, then switch) is equally defensible and differs by exactly one sample -- which export verification scores as a whole class index, not as a rounding error.

The state is held as class POSITIONS in [0, K); the index base is added once, on the way out. That keeps every comparison in the body a comparison against a small whole constant, which is what makes the fixed-point targets exact rather than approximately right.

Sample results#

Debounced Decision — Step: 0 -> 1 at t = 1 sDebounced Decision — Step: 0 -> 1 at t = 1 s00.51012345t (s)in ICoreDouble-Out-0out ICoreDouble-Out-0out ICoreDouble-Out-1

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0 … 0
rampRamp: slope 1 from t = 00 … 3
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias0 … 1
tableRepeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample0 … 1

Plotted: step — Step: 0 -> 1 at t = 1 s

Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Machine_Learning__Postprocessing__Debounced_Decision.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).