Generated reference › LSTM Cell — Machine Learning/Neural Networks
kind: generated#block#machine-learning-neural-networks

LSTM Cell — Machine Learning/Neural Networks

Machine_Learning/Neural_Networks/LSTM_Cell · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

LSTM Cell

Machine Learning / Neural Networks

One long short-term memory step, evaluated at inference – torch.nn.LSTMCell:

i = σ(Wiiu + bii + Whih + bhi)   f = σ(Wifu + bif + Whfh + bhf)
g = tanh(Wigu + big + Whgh + bhg)   o = σ(Wiou + bio + Whoh + bho)
c' = f·c + i·g    h' = o·tanh(c')

The cell state c is the long-term path: the forget gate scales what is already there and the input gate decides how much of the candidate joins it, with no squashing in between. That additive path is why an LSTM holds information over far more steps than a Simple RNN Cell, whose state passes through a tanh every step.

Ports

  • u – the input sample, a column [m,1], m being the COLUMNS of Input Weights.
  • h – the new hidden state, [n,1], where n is the ROWS of Input Weights divided by four. This is the cell's output in the usual sense.
  • c – the new cell state, [n,1]. Exposed because LSTMCell returns it and a stacked cell needs it; ignore it if you are using one cell as a layer.

Parameters

  • Input Weights[4n,m], the four input matrices stacked i, f, g, ocell.weight_ih's own layout, so it pastes in without splitting.
  • Recurrent Weights[4n,n], stacked the same way (cell.weight_hh).
  • Input Bias[4n,1] (cell.bias_ih).
  • Recurrent Bias[4n,1] (cell.bias_hh). Unlike GRU Cell, these two could be added together without changing the answer – see Notes – but they are taken separately so a PyTorch export pastes straight in.
  • Initial Hidden State[n,1].
  • Initial Cell State[n,1]. A trained model almost always starts both at zero; set them otherwise only if you are resuming a sequence.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. Being discrete-only, a non-positive value falls back to the model's global sampling time.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every weight is baked in at full setprecision(17); both state vectors are carried in each backend's own persistent form, seeded from the two initial-state configs.

The three HDL targets are simulation-only: sigmoid and tanh are transcendental. PLC Structured Text has no TANH, so it is emitted through 2 ÷ (1 + EXP(−2z)) − 1.

Simulink bridge

None. Simulink's LSTM lives inside its Deep Learning blocks, which take a trained network object rather than weight matrices, and no config value can carry an object across the bridge. The bridge reports the block rather than dropping it silently, and it has no parity testbench, which is the documented consequence of Support::None.

Notes

  • Why the biases are separate even though they need not be. Every LSTM gate only ever adds its two biases, so folding them is exact – unlike GRU Cell, where the reset gate multiplies one of them and folding is wrong. They are kept apart here for convenience and consistency, not correctness: a PyTorch export gives you bias_ih and bias_hh and you paste both.
  • h' depends on the NEW c, not the old one. That is the one ordering this block must get right, and every backend computes c' first and feeds it into tanh for h'.
  • Stateful and discrete by nature, so the block declares itself discrete-only, and carries no state space – the gates are nonlinear.
  • Both states are read before either is written. The generated code builds the whole new h and c before storing either, except on the three HDL targets where registered state gives that for free.

Code facts#

FactValue
registered typeMachine_Learning/Neural_Networks/LSTM_Cell
familyMachine_Learning/Neural_Networks
solver environment classICoreBlock_0_Machine_Learning_1_Neural_Networks_2_LSTM_Cell
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Neural_Networks/LSTM_Cell/ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_LSTM_Cell.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Neural_Networks/LSTM_Cell/ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_LSTM_Cell.h
default size on canvas130 × 92 px
ports at insert1 in, 2 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoubleu
2outICoreDoubleh
3outICoreDoublec

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Input Weights[0.5 -0.3 0.2; 0.4 0.15 -0.25; -0.35 0.45 0.1; 0.2 -0.5 0…
Recurrent Weights[0.3 -0.2; 0.25 0.4; -0.1 0.35; 0.45 -0.3; 0.2 0.5; -0.4 …
Input Bias[0.05; -0.1; 0.15; -0.05; 0.2; -0.15; 0.1; -0.2]
Recurrent Bias[-0.1; 0.05; -0.2; 0.1; -0.05; 0.25; -0.15; 0.3]
Initial Hidden State[0; 0]
Initial Cell State[0; 0]

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): no Simulink equivalent that could carry the weights: its LSTM exists only inside the Deep Learning blocks, which take a trained network OBJECT rather than weight matrices, and no config value crosses the bridge as an object

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

  • B0 every stimulus in the sample errored — cross-checks skipped

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

LSTM Cell — four gates, two state vectors, two outputs i = sigmoid(Wii*u + bii + Whi*h + bhi) f = sigmoid(Wif*u + bif + Whf*h + bhf) g = tanh (Wig*u + big + Whg*h + bhg) o = sigmoid(Wio*u + bio + Who*h + bho) c' = f*c + i*g h' = o * tanh(c')

Simple_RNN_Cell's state surface, applied twice. See its header for the ten persistent forms and for why the three registered HDL targets get read-before-write free while the other eight must build into temporaries -- with two state vectors that matters twice as much, and h' additionally depends on the NEW c, which is the one ordering this block has to get right.

HDL is SIMULATION-ONLY real (sigmoid, tanh); PLC ST has no TANH and uses the EXP identity.

Sample results#

No stimulus produced a sampled output in this rig — Invalid input size at: ICore Blocks/Home/LSTM Cell. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.

Category unsampled · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60

Sample data: docs/generated/samples/Machine_Learning__Neural_Networks__LSTM_Cell.json