Sinc — Control Systems/Waveform Functions
Control_Systems/Waveform_Functions/Sinc · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Sinc
Control Systems / Waveform Functions
The normalized cardinal sine, entry by entry: y = sin(π·x) / (π·x), and y = 1 where x = 0.
It is the interpolation kernel of the sampling theorem and the impulse response of an ideal brick-wall lowpass: unity at the origin, zero at every nonzero integer, and bounded by 1.
Ports
- Input – the argument x of the relation above, of any size [m,n], applied entry by entry. It is a plain number, not a time in seconds: feed it t·f to place the first zero crossings at ±1/f.
- Output – the result y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to tune, so nothing is exposed as a parameter on the generated core.
π is written into every core as one decimal literal rather than read from the target's own constant, so the ten exports agree with this block's own arithmetic to the last bit.
The three HDL targets are simulation-only. There is no fixed-point
sine in the Q16.16 datapath to call, and a quotient whose numerator and
denominator both vanish at the origin has no useful fixed-point form there, so
the generated cores convert at the port boundary and evaluate in
real arithmetic – correct in simulation, but not offered as
synthesizable.
Simulink bridge
None. There is no cardinal-sine block in the Simulink standard
library; MATLAB offers it as the Signal Processing Toolbox function
sinc, which is not a block and has no library path a diagram could
name. A model carrying this block is reported rather than silently dropped when
it crosses, and no configuration of it can cross either – including
"Sampling Time (s)", which has no counterpart to be written to.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- Even: sinc(−x) = sinc(x).
- The value at the origin is decided by an exact comparison against zero, not by a tolerance band. Every other argument goes through the quotient, which is accurate across the whole range of a double.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Waveform_Functions/Sinc |
| family | Control_Systems/Waveform_Functions |
| solver environment class | ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Sinc |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Sinc/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Sinc.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Sinc/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Sinc.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): the cardinal sine is a Signal Processing Toolbox FUNCTION (sinc), not a Simulink library block, so there is no path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Sinc -- y = sin(pi*x) / (pi*x), and y = 1 at x = 0 The normalized cardinal sine. Algebraic and stateless, one input, one output, no parameters. No state space -- see the header for why.
Two things every target has to spell identically, because the ten exported cores are compared against the C++ relation below:
- pi is embedded as ONE decimal literal rather than read from each language's own
constant. The values agree today; the literal makes them agree by construction.
- the singularity is tested as an EXACT zero, so the quotient is used everywhere
else and no tolerance band flattens the values near the origin.
The three hardware-description targets evaluate in floating point and are offered as simulation-only: the Q16.16 datapath they otherwise use carries no sine, and a quotient whose numerator and denominator both approach zero has no useful fixed-point form near the origin.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -3.898e-17 |
| 0.4 | 0.5 | 0.6366 |
| 0.8 | -2 | -3.898e-17 |
| 1.2 | 0.5 | 0.6366 |
| 1.6 | -2 | -3.898e-17 |
| 2 | 0.5 | 0.6366 |
| 2.4 | -2 | -3.898e-17 |
| 2.8 | 0.5 | 0.6366 |
| 3.2 | -2 | -3.898e-17 |
| 3.6 | 0.5 | 0.6366 |
| 4 | -2 | -3.898e-17 |
| 4.4 | 0.5 | 0.6366 |
| 4.8 | -2 | -3.898e-17 |
| 5.2 | 0.5 | 0.6366 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 3.898e-17 … 1 |
ramp | Ramp: slope 1 from t = 0 | -0.2162 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 9.794e-6 … 1 |
step | Step: 0 -> 1 at t = 1 s | 3.898e-17 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 87d3936094fa2ff37688c80c5846c4dd08d6a27d · produced by docsSample --out <folder> --blocks Sinc Rectangular_Pulse Triangular_Pulse Gaussian_Monopulse Gaussian_RF_Pulse Dirichlet_Function --steps 60 · data docs/generated/samples/Control_Systems__Waveform_Functions__Sinc.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).