Dirichlet Function — Control Systems/Waveform Functions
Control_Systems/Waveform_Functions/Dirichlet_Function · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Dirichlet Function
Control Systems / Waveform Functions
The Dirichlet kernel of order N – the periodic sinc – evaluated entry by entry:
y = sin(N·x/2) / (N·sin(x/2))
It is the frequency response of an N-point rectangular window, so it is what the main lobe and side lobes of an unwindowed spectrum actually are. It is periodic in 2π for even N and 4π for odd N, and bounded by 1.
The denominator vanishes at every multiple of 2π, not only at the origin. The limit there is +1 or −1 alternately, and the sign is exactly sign(cos(x·(N+1)/2)), which is the value the block returns whenever sin(x/2) has collapsed.
Ports
- Input – the argument x of the relation above, in radians, of any size [m,n], applied entry by entry.
- Output – the result y, of the SAME size [m,n], in [−1, +1]. The block never reshapes a signal.
Parameters
- Order N – the kernel order, a scalar whole number of at least 1. It is the length of the rectangular window whose response this is; a non-scalar, fractional or smaller value is reported and stops the run. Default 3. N = 1 is the constant 1.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.
The order is structural: N, N/2 and (N+1)/2 are folded once at export time and written into the body as decimal literals, so the generated core carries no tunable parameter. Re-export after changing the order.
The three HDL targets are simulation-only. There is no fixed-point sine
in the Q16.16 datapath to call, and the tolerance band that selects the branch is
ten orders of magnitude narrower than one quantum, so the choice it makes has no
fixed-point meaning; the generated cores convert at the port boundary and
evaluate in real arithmetic instead. Correct in simulation, and not
offered as synthesizable.
Simulink bridge
None. The Simulink standard library has no Dirichlet kernel block:
MathWorks offers it as the Signal Processing Toolbox function diric,
which is not a block and has no library path a diagram could name. A model
carrying this block is reported rather than silently dropped when it crosses, and
neither "Order N" nor "Sampling Time (s)" has a counterpart to be written to.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- Even: y(−x) = y(x).
- The singularity test is a tolerance band, not an exact comparison. Only x = 0 is an exactly representable multiple of 2π, so at the others the denominator comes out tiny rather than zero, and dividing by it would return a number the size of the reciprocal of the rounding error rather than a value near ±1. The band is 10⁴ double epsilons wide. The sibling Sinc block tests for an exact zero instead, because its only singularity is at the origin.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Waveform_Functions/Dirichlet_Function |
| family | Control_Systems/Waveform_Functions |
| solver environment class | ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Dirichlet_Function |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Dirichlet_Function/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Dirichlet_Function.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Dirichlet_Function/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Dirichlet_Function.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Order N | 3 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): the Dirichlet kernel is a Signal Processing Toolbox FUNCTION (diric), not a Simulink library block, so there is no path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Dirichlet Function -- y = sin(N*x/2) / (N*sin(x/2)), the periodic sinc Algebraic and stateless. No state space -- see the header, which also explains why the singularity test here is a tolerance band while the sibling Sinc block's is an exact comparison against zero.
Every constant the two branches need is folded once, here, and embedded in each generated core as a decimal literal: N as a real, N/2, and (N+1)/2. No target re-derives them from the order, so none of the ten rounds the derivation differently.
The three hardware-description targets evaluate in floating point and are offered as simulation-only. The Q16.16 datapath carries no sine to call, and the tolerance band is ten orders of magnitude narrower than one quantum, so the branch it selects has no fixed-point meaning at all.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 0.0559 |
| 0.4 | 0.5 | 0.9184 |
| 0.8 | -2 | 0.0559 |
| 1.2 | 0.5 | 0.9184 |
| 1.6 | -2 | 0.0559 |
| 2 | 0.5 | 0.9184 |
| 2.4 | -2 | 0.0559 |
| 2.8 | 0.5 | 0.9184 |
| 3.2 | -2 | 0.0559 |
| 3.6 | 0.5 | 0.9184 |
| 4 | -2 | 0.0559 |
| 4.4 | 0.5 | 0.9184 |
| 4.8 | -2 | 0.0559 |
| 5.2 | 0.5 | 0.9184 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0.6935 … 1 |
ramp | Ramp: slope 1 from t = 0 | -0.3328 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0.6935 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0.6935 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 87d3936094fa2ff37688c80c5846c4dd08d6a27d · produced by docsSample --out <folder> --blocks Sinc Rectangular_Pulse Triangular_Pulse Gaussian_Monopulse Gaussian_RF_Pulse Dirichlet_Function --steps 60 · data docs/generated/samples/Control_Systems__Waveform_Functions__Dirichlet_Function.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).