Real Cepstrum — Control Systems/Transforms

Control_Systems/Transforms/Real_Cepstrum · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Real Cepstrum

Control Systems / Transforms

The inverse transform of the log magnitude spectrum of the window on the input port – MATLAB's rceps:

y = real( ifft( log( abs( fft(u) ) ) ) )

The logarithm is what makes this a cepstrum rather than an autocorrelation: a product of spectra becomes a sum of cepstra, so a signal and the channel it passed through separate into different quefrency ranges instead of convolving. Pitch, echo delay and formant/excitation separation are what it is reached for. The index of the output is a quefrency – a time, in samples – not a frequency.

Because u is real, log|X| is even in k and the inverse transform of it is real: the block returns N real numbers, with no imaginary half to carry.

Ports

u – the window, a vector: an [N,1] column or a [1,N] row, with N from 1 to 32. N is taken from the port; there is no length parameter.
y – the real cepstrum, the SAME shape and length as the input.

Parameters

Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

There is no other parameter, and that is the transform rather than an omission: once N is known the whole map is fixed.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The 3×N×N cosine and sine coefficients are derived when the port size settles and inlined into every emitted body, so no core computes a sine or a cosine – it multiplies, adds, and takes N logarithms. That also means the window length bounds the size of the emitted core, which is why it stops at 32.

The three HDL targets are simulation-only: they compute in real and quantize only at the port boundary. A logarithm has no place in a Q16.16 datapath, so the alternative would have been no HDL column at all. VHDL additionally gets a procedure with local variables rather than architecture-scope signals, because a signal written inside a clocked process reads back as its pre-clock contents and the N log values are needed in the same tick they are computed in.

Their residual is larger than most blocks' and the logarithm is why. The port still quantizes to Q16.16, and d(ln|X|)/d|X| = 1/|X|, so a bin that lands near zero turns one port quantum into a much larger absolute error at that quefrency. Measured over 1001-sample export-verification runs the three of them come back between 0.03 % and 0.46 % against a 1 % band, against 1×10⁻¹⁴ or better on the six software targets – and the figure MOVES between runs, because the verification stimulus is drawn fresh each time and which bin comes closest to zero changes with it. That is the block meeting the port's resolution, not the core drifting.

Simulink bridge

Import and export, mapped to dspxfrm3/Real Cepstrum – the DSP System Toolbox block, not a core Simulink one. It has no semantic parameter to carry: inheritFFT is always emitted as on, which makes the transform length the input frame's, exactly as it is taken from the input port here, and the block's N is then unused.

Unlike DCT, the Simulink block accepts any window length – measured on 5-, 6- and 8-point frames, all three agreeing with rceps to 5.6×10⁻¹⁷ – so there is no power-of-two restriction to report here.

"Sampling Time (s)" does not cross. dspxfrm3/Real Cepstrum defines no SampleTime parameter: set_param on it answers "Real Cepstrum block (mask) does not have a parameter named 'SampleTime'", which is a hard error that aborts a generated script rather than degrading. The rate stays on the ICore side, and a block configured with an explicit positive rate reports that it did not cross.

Notes

Algebraic, with no state: the whole window arrives on the port, so one step completes one transform and nothing is held between samples.
No state space, and not only because a fixed matrix over a window is not an A/B/C/D pair evolving in time: this map is not linear in the input at all, the logarithm sitting in the middle of it.
A bin of exactly zero gives −infinity, and that is the transform rather than a defect – MATLAB's rceps does the same. A constant window is the case that reaches it: every bin but the first is then exactly zero. Worth knowing when a model holds a signal still.
The minimum-phase reconstruction is not here. MATLAB's rceps has a second output, and the Simulink block does not – it has one input and one output, measured – so a second port would have nothing to cross to.
Real Cepstrum vs. FFT. Reach for FFT when the spectrum itself is wanted; it returns Re and Im on two ports and cannot bridge to Simulink for exactly that reason. This block's answer is real, which is what lets it bridge.

Code facts#

Fact	Value
registered type	`Control_Systems/Transforms/Real_Cepstrum`
family	`Control_Systems/Transforms`
solver environment class	`ICoreBlock_0_Control_Systems_1_Transforms_2_Real_Cepstrum`
source	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Transforms/Real_Cepstrum/ICoreBlock_0_Control_Systems_1_Transforms_2_Real_Cepstrum.cpp`
header	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Transforms/Real_Cepstrum/ICoreBlock_0_Control_Systems_1_Transforms_2_Real_Cepstrum.h`
default size on canvas	150 × 80 px
ports at insert	1 in, 1 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

#	Direction	Signal type	Description label
1	in	`ICoreDouble`	u
2	out	`ICoreDouble`	y

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

No config variable beyond the Sampling Time (s) every block carries.

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::Both`
Simulink path	`dspxfrm3/Real Cepstrum`
port-count rule	`PortsParam::None`
`SampleTime` parameter	no — the counterpart defines none; the rate stays on the ICore side
always set	`inheritFFT` = `on`

Caveat (shown to the user): maps to the DSP System Toolbox's Real Cepstrum, which computes the same transform (SIMULATED on 5-, 6- and 8-point frames, all three agreeing with MATLAB's rceps to 5.6e-17). The transform length is not a parameter on either side: inheritFFT is always emitted as 'on', which takes it from the input frame exactly as this block takes it from the input port, and the Simulink block's N is then unused. UNLIKE DCT, the counterpart accepts any window length, so there is no power-of-two caveat to report. And it has NO SampleTime parameter - set_param answers "Real Cepstrum block (mask) does not have a parameter named 'SampleTime'" - so the rate stays on the ICore side. MATLAB's rceps has a second output, the minimum-phase reconstruction; the Simulink block does not, so this block has one output and there is nothing missing from the crossing

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Real Cepstrum -- the inverse transform of the log magnitude spectrum (MATLAB rceps) y = real( ifft( log( abs( fft(u) ) ) ) )

The LOG is what makes it a cepstrum rather than an autocorrelation: a product of spectra becomes a SUM of cepstra, so a signal and the channel it went through separate into different quefrency ranges instead of convolving. Pitch, echo delay and formant/excitation separation are what it is reached for.

TWO MATRIX PRODUCTS WITH A LOG BETWEEN THEM. log|X[k]| is real and EVEN in k whenever u is real, so the inverse transform of it is real and needs cosines only:

re[k] = SUM over n of u[n] * cos(2*pi*k*n/N) im[k] = -SUM over n of u[n] * sin(2*pi*k*n/N) L[k] = 0.5 * ln( re[k]^2 + im[k]^2 ) y[n] = (1/N) * SUM over k of L[k] * cos(2*pi*k*n/N)

The 3*N*N coefficients depend on the window LENGTH and on nothing else, so they are derived once, when the input port's size settles, and every target inlines them. No emitted core computes a sine or a cosine; it multiplies, adds, and takes N logarithms.

⚠ 0.5*ln(p) RATHER THAN ln(sqrt(p)). One transcendental instead of two, the same value to within a rounding, and - the reason it is written down - the SAME expression in all ten backends, so none of them can drift by having chosen the other spelling.

⚠ THE ANGLE IS REDUCED MODULO N BEFORE THE TRIG CALL, exactly as FFT does it. k*n reaches (N-1)^2 and a cosine of an argument in the thousands has lost most of its low-order accuracy to argument reduction, while exp(-2*pi*i*k*n/N) is periodic in k*n with period N -- so ((k*n) mod N) is the same number computed from a small angle.

⚠ A BIN OF EXACTLY ZERO GIVES -INFINITY, and that is the transform rather than a defect: MATLAB's rceps does the same, because log(0) is what it is. A CONSTANT window is the case that reaches it -- every bin but the first is then exactly zero -- which is worth knowing when a rig or a model holds a signal still.

⚠ MEASURED AGAINST R2026a rather than asserted. dspxfrm3/Real Cepstrum was SIMULATED on 5-, 6- and 8-point windows and agreed with rceps() to 5.6e-17 on all three; rceps() itself was checked against real(ifft(log(abs(fft(x))))) on the same data and agreed to the last bit. ⚠ And UNLIKE DCT, THE SIMULINK BLOCK ACCEPTS ANY WINDOW LENGTH -- the 5- and 6-point runs are the measurement that says so, which is why this block's entry carries no power-of-two caveat where DCT's does.

Sample results#

7 sample(s) were non-finite (nan/inf) and are absent from the plot; they are in the table below and in the JSON.

t	in ICoreDouble-Out-0	out ICoreDouble-Out-0
0	-2	0.6931
0.4	0.5	-0.6931
0.8	-2	0.6931
1.2	0.5	-0.6931
1.6	-2	0.6931
2	0.5	-0.6931
2.4	-2	0.6931
2.8	0.5	-0.6931
3.2	-2	0.6931
3.6	0.5	-0.6931
4	-2	0.6931
4.4	0.5	-0.6931
4.8	-2	0.6931
5.2	0.5	-0.6931

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

Stimulus	What it is	Output range
`impulse`	Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)	0 … 0
`ramp`	Ramp: slope 1 from t = 0	-2.303 … 1.758
`sine`	Sine Wave: amplitude 1, 2 rad/s, no phase, no bias	-3.698 … -9.793e-6
`step`	Step: 0 -> 1 at t = 1 s	0 … 0

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit 7bd89ba81 · produced by docsSample --out <folder> --blocks Real_Cepstrum --steps 60 · data docs/generated/samples/Control_Systems__Transforms__Real_Cepstrum.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).