Piecewise Expression — Control Systems/Symbolic
Control_Systems/Symbolic/Piecewise_Expression · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Piecewise Expression
Control Systems / Symbolic
Evaluates a conditional expression of the input at every sample: the
first condition that holds selects its value, and the otherwise value
answers when none does. This is MATLAB's piecewise, written in
MATLAB's own syntax:
piecewise(x < 0, 0, x < 1, x^2, 2*x - 1)
The text is read once, when the configuration loads. Every value, and
each side of every condition, goes through the symbolic engine exactly as a
Symbolic Expression's does, so a constant such as pi/4 is
folded once rather than recomputed per sample. What runs per sample is an
if / else-if / else chain with one plain expression per branch, and only
the branch that is taken is evaluated.
The factory setting above is a smooth ramp: 0 below zero, a parabola on [0, 1) and the line 2x − 1 above it. The pieces meet with the same value and the same slope at both joins, so the block out of the library is a worked example of a piecewise function with no jump.
Ports
- x – the variables, a vector of n entries (a column [n,1] or a row [1,n]) where n is the number of names in Variables: entry k is the k-th name. A Mux in front builds it from scalar signals; with one variable the input is a scalar.
- y – the selected value, a scalar [1,1].
Parameters
- Expression – ONE call,
piecewise(cond1, value1, cond2, value2, ..., otherwise): conditions and values alternating, and the otherwise value last. A condition compares two expressions with< <= > >= == ~=and combines comparisons with&(and),|(or) and~(...)(not). A chain such as-1 < x <= 1is a range, as MATLAB's symbolic reader has it: every adjacent pair must hold. A value, and each side of a comparison, may use numbers, the declared variables,pi,+ - * / ^, parentheses and the functionssin cos tan sec csc cot asin acos atan acot sinh cosh tanh asinh acosh atanh exp log log2 log10 sqrt abs sign heaviside. - Variables – the names of the input's entries, in order, separated
by spaces or commas:
x y. Each is a MATLAB identifier, none may repeat, and none may be a function name orpi,e,i,j,Inf,NaNoreps. At most 12. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. Each carries the chain as that language's own
if statement – if/elif/else,
if/elseif/else/end, IF/ELSIF/ELSE/END_IF,
if/elsif/else/end if, if ... begin/end – with one
assignment per branch and every constant folded to 17 significant digits, and in
each of them only the branch taken is evaluated. The three HDL targets are
simulation-only real arithmetic, quantized to Q16.16 only at
the ports: a comparison of arbitrary expressions is not a fixed-point
datapath.
Simulink bridge
None (Support::None). piecewise is a Symbolic
Math Toolbox function, and that toolbox ships no Simulink library at all, so
there is no library path a diagram could name; the bridge reports this block
rather than dropping it, and it therefore has no parity testbench. Code
export verification covers it across all ten languages. No configuration crosses,
including "Sampling Time (s)".
Notes
- ⚠ The otherwise value is REQUIRED here, where MATLAB makes it optional.
Without one MATLAB answers NaN wherever no condition holds, and a NaN is
not a value the HDL and PLC targets can carry, so a
piecewisethat ends on a value's condition is refused with that reason. To reproduce MATLAB's answer exactly, make the otherwise value something the rest of the diagram can recognise. - The first condition that holds wins, as in MATLAB: conditions may overlap, and their ORDER is part of the expression.
- ⚠ A chain is a RANGE here, as it is in MATLAB's symbolic reader
– and not as in MATLAB's numeric one, which reads
-1 < x < 1as(-1 < x) < 1.-1 < x < y < 1means all three adjacent comparisons hold. A chain holding==or~=is refused: MATLAB accepts one and then cannot evaluate it. &&and||are refused, because MATLAB refuses them on a symbolic condition ("Conversion to logical from sym is not possible"); write&and|. And~must negate a condition: MATLAB reads~x > 1as(~x) > 1, so write~(x > 1).- A condition is not a number and a number is not a condition: a value
such as
(x > 0)*xand a condition such asx & yare refused, as is apiecewisenested inside another expression – add a branch instead. - ⚠ A jump is a jump in every target: where the pieces do not meet, the output steps as the input crosses the boundary, and the three HDL targets – which see the input quantized at the port – can land on the other side of it near the join. That is the function, not the export.
- Comparisons follow IEEE rules: any comparison with a NaN input is false, so a NaN input falls through to the otherwise value.
- Algebraic, with no state: the output depends only on the current input.
- No state space: a branch is not linear, so model reduction correctly declines the block.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Symbolic/Piecewise_Expression |
| family | Control_Systems/Symbolic |
| solver environment class | ICoreBlock_0_Control_Systems_1_Symbolic_2_Piecewise_Expression |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Symbolic/Piecewise_Expression/ICoreBlock_0_Control_Systems_1_Symbolic_2_Piecewise_Expression.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Symbolic/Piecewise_Expression/ICoreBlock_0_Control_Systems_1_Symbolic_2_Piecewise_Expression.h |
| default size on canvas | 160 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | x |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Expression | piecewise(x < 0, 0, x < 1, x^2, 2*x - 1) | — |
Variables | x | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): piecewise is a Symbolic Math Toolbox function, and that toolbox ships no Simulink library at all, so there is no library path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Piecewise Expression -- piecewise, compiled once at config load into an if/else chain y = piecewise(c1, v1, c2, v2, ..., otherwise)
The first condition that holds selects its value, and the otherwise value answers when none does -- MATLAB's order and MATLAB's syntax, typed as the block's Expression. The text is read ONCE, when the configuration loads: every value and each side of every relation goes through the console's symbolic engine exactly as a Symbolic Expression's does, and the conditions' structure is the family reader's.
What every target carries is an IF / ELSE-IF / ELSE CHAIN, one assignment per branch, and not a conditional expression -- MATLAB and VHDL have none, and one shape that is right in all ten beats two. The chain is LAZY in all of them, as the C++ reference is: only the branch taken is evaluated, so a value that is out of its domain on another branch (sqrt of a negative, a log of zero) costs nothing where it is not selected.
The reading, the sizing contract, compute_h and all ten generators are ICoreSymbolicBlockBase's; the reader and the statement printer are ICoreSymbolicProgram's (compilePiecewise, renderStatements). This file is what is genuinely this block's: its operation, its ports, its configs, its description, its icon and its Simulink entry.
⚠ THE OTHERWISE VALUE IS REQUIRED. MATLAB makes it optional and answers NaN where no condition holds; NaN is not a value the three HDL targets or PLC Structured Text can carry, so a piecewise without one is refused with that reason rather than given a stand-in.
VERIFIED OUTSIDE ICORE, because code-export verification compares the block with itself: the block's own evaluation was compared with MATLAB R2026a's
subs(piecewise(...))on the same expressions at the same points -- the toolbox-blocks plan's row records the counts.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 0 |
| 0.4 | 0.5 | 0.25 |
| 0.8 | -2 | 0 |
| 1.2 | 0.5 | 0.25 |
| 1.6 | -2 | 0 |
| 2 | 0.5 | 0.25 |
| 2.4 | -2 | 0 |
| 2.8 | 0.5 | 0.25 |
| 3.2 | -2 | 0 |
| 3.6 | 0.5 | 0.25 |
| 4 | -2 | 0 |
| 4.4 | 0.5 | 0.25 |
| 4.8 | -2 | 0 |
| 5.2 | 0.5 | 0.25 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 10.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0.9991 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 28c7e7537 · produced by docsSample --out <folder> --blocks Piecewise_Expression --steps 60 · data docs/generated/samples/Control_Systems__Symbolic__Piecewise_Expression.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).