Substring — Control Systems/Strings
Control_Systems/Strings/Substring · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Substring
Control Systems / Strings
Takes a piece of the incoming text: y = the len bytes of u starting at byte idx, counting from 1. "abcdef" from 2 for 3 is "bcd"; from 5 for 4 is "ef", because a length that runs off the end is cut at the end.
Ports
- u (
str,ICoreString) – the text. - idx – where the piece starts, counting the first byte as 1. One number [1,1]; any numeric type is accepted, so String Find's position can drive it directly.
- len – how many bytes the piece has. One number [1,1]; any numeric type is accepted, so String Length can drive it directly.
- Output – the piece y (
str,ICoreString), one value.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Every input has an answer
- A fraction is cut down to the whole number below it: idx 2.7 is 2.
- idx below 1 is read as 1; idx past the end of the text gives empty text.
- len below 0 is read as 0, which gives empty text; len past the end of the text is cut at the end.
Simulink stops the whole simulation on an idx of 0 or an idx past the end; this block answers instead, and agrees with Simulink everywhere Simulink answers.
Bytes, not characters
idx and len count bytes of UTF-8, as String Length and String Find do. For ordinary English text those are characters. On accented or non-Latin text a piece can start or end in the middle of a character; C and C++ keep the half-character's bytes, while Java, Python, MATLAB and Rust drop or replace them, so that is the one case where targets can differ.
Code export
C, C++, Python, MATLAB, Java and Rust all take the same bytes by the same rules.
VHDL, Verilog and SystemVerilog do not carry text, and PLC Structured Text is not supported either: the language has a string type, but the check that runs an exported core cannot read one back. An export to any of these four stops and names this block and the reason.
Simulink bridge
Import and export, mapped to simulink/String/Substring. Simulink
counts characters where this block counts bytes, which is the same number for
plain English text. Simulink's option to take everything from idx to the end
(which removes its len input) is not offered here: it is always written as off,
and a Simulink model that turns it on does not cross correctly. Simulink's idx
and len must be integer types, so an exported diagram feeding them doubles
needs a Data Type Conversion on the Simulink side. The output data type is
always string and is written as a fixed setting. The Simulink block
has no sampling-time setting of its own, so a positive Sampling Time
(s) stays on this side and is reported rather than written.
Notes
- Algebraic, with no state: the output depends only on the current inputs.
- An unconnected text input is empty text, so the output is empty.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Strings/Substring |
| family | Control_Systems/Strings |
| solver environment class | ICoreBlock_0_Control_Systems_1_Strings_2_Substring |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/Substring/ICoreBlock_0_Control_Systems_1_Strings_2_Substring.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/Substring/ICoreBlock_0_Control_Systems_1_Strings_2_Substring.h |
| default size on canvas | 90 × 80 px |
| ports at insert | 3 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreString | u |
| 2 | in | ICoreDouble | idx |
| 3 | in | ICoreDouble | len |
| 4 | out | ICoreString | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/String/Substring |
| port-count rule | PortsParam:: |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): idx and len are 1-based and count CHARACTERS in Simulink and BYTES here (the same for ASCII). Simulink stops the simulation on idx 0 or idx past
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Substring -- a piece of the text, from a start index for a length y = u(idx .. idx+len-1), 1-based, over BYTES of UTF-8 as the rest of this family counts, and TOTAL: with L the text's length in bytes, start = floor(idx), read as 1 below 1 -> y = "" when start > L count = floor(len), read as 0 below 0 -> clipped at the end of the text Simulink answers the same wherever it answers at all; it stops the simulation on idx 0 and on an idx past the end (measured), which is where this block answers "" or starts at 1.
The comparisons are written so that NaN falls on the safe side (!(x >= 1)), and every value is compared as a DOUBLE before it is converted, so no target converts a value that does not fit its integer type.
Sample results#
This block carries a ICoreString signal, whose value is text rather than a number and is not something a plot has an axis for. The samples are in the table below, exactly as the run recorded them.
| t | in ICoreString-Out-0 | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreString-Out-0 |
|---|---|---|---|---|
| 0 | u0 | -2 | -2 | |
| 0.4 | u0 | 0.5 | 0.5 | |
| 0.8 | u0 | -2 | -2 | |
| 1.2 | u0 | 0.5 | 0.5 | |
| 1.6 | u0 | -2 | -2 | |
| 2 | u0 | 0.5 | 0.5 | |
| 2.4 | u0 | -2 | -2 | |
| 2.8 | u0 | 0.5 | 0.5 | |
| 3.2 | u0 | -2 | -2 | |
| 3.6 | u0 | 0.5 | 0.5 | |
| 4 | u0 | -2 | -2 | |
| 4.4 | u0 | 0.5 | 0.5 | |
| 4.8 | u0 | -2 | -2 | |
| 5.2 | u0 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | — |
ramp | Ramp: slope 1 from t = 0 | — |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | — |
step | Step: 0 -> 1 at t = 1 s | — |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 6280f52f3 · produced by docsSample --out <folder> --blocks Rational_Resample,Three_Axis_Accelerometer,Three_Axis_Gyroscope,Three_Axis_Inertial_Measurement_Unit,Eclipse_Shadow_Model,To_String,String_To_ASCII,ASCII_To_String,Substring,String_Constant,String_Concatenate,String_Compare,String_Length --steps 60 · data docs/generated/samples/Control_Systems__Strings__Substring.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).