String To ASCII — Control Systems/Strings
Control_Systems/Strings/String_To_ASCII · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
String to ASCII
Control Systems / Strings
Turns text into the codes of its characters: y = [code of each character
of u, then zeros], a row of fixed width N. "abc" with N = 6 is
[97 98 99 0 0 0].
Ports
- Input – the text u (
str,ICoreString). - Output – the codes y (
u8,ICoreUInt8), a row [1,N]: one code per character from the left, zeros after the last character.
Parameters
- Output vector size – N, the width of the output row, a whole number of at least 1 (values below 1 are read as 1, a fraction is cut down). Text with more than N characters is cut to its first N; shorter text is padded with zeros. Default 31, as in Simulink.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Codes, not bytes
Each code is a character's code, 0 to 255 – the Latin-1
character set, which is the set Simulink's text is made of. So "é" is
one code, 233, even though it is two bytes of text here. A character outside
Latin-1 (a Chinese character, an emoji) has no code in that set and is written
as 63, the code of ?.
Code export
C, C++, Python, MATLAB, Java and Rust all answer the same codes, padded and cut the same way.
VHDL, Verilog and SystemVerilog do not carry text, and PLC Structured Text is not supported either: the language has a string type, but the check that runs an exported core cannot read one back. Since this block's input is always text, an export to any of these four stops and names this block and the reason.
Simulink bridge
Import and export, mapped to simulink/String/String to ASCII.
"Output vector size" crosses as OutputVectorSize. Simulink cuts a
text longer than N the same way and adds a warning; this block cuts it
silently. The Simulink block has no sampling-time setting of its own, so a
positive Sampling Time (s) stays on this side and is reported rather
than written.
Notes
- Algebraic, with no state: the output depends only on the current input.
- ASCII to String is the inverse: its output fed back here gives the same codes, up to the first zero.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Strings/String_To_ASCII |
| family | Control_Systems/Strings |
| solver environment class | ICoreBlock_0_Control_Systems_1_Strings_2_String_To_ASCII |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/String_To_ASCII/ICoreBlock_0_Control_Systems_1_Strings_2_String_To_ASCII.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/String_To_ASCII/ICoreBlock_0_Control_Systems_1_Strings_2_String_To_ASCII.h |
| default size on canvas | 90 × 60 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreString | — |
| 2 | out | ICoreUInt8 | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Output vector size | 31 | OutputVectorSize |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/String/String to ASCII |
| port-count rule | PortsParam:: |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Output vector size | OutputVectorSize | passes through |
Caveat (shown to the user): codes are Latin-1 CHARACTER codes on both sides (Simulink's text is
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
String to ASCII -- text in, a fixed-width row of character codes out y = [code(c1) code(c2) ... 0 0], width N from "Output vector size", cut at N. The output is an ICoreUInt8 ROW, 1 x N -- the shape Simulink's block answers (To Workspace records it as time x 31 at the default, measured) -- and it is sized from config, so the maps are loaded in initializePortSignalSize() as Gain's are.
The one rule every generator repeats: decode the UTF-8 text into characters; a character with a code up to 255 answers that code, anything else answers 63 ('?'). See the header for why codes rather than bytes.
Sample results#
This block carries a ICoreString signal, whose value is text rather than a number and is not something a plot has an axis for. The samples are in the table below, exactly as the run recorded them.
| t | in ICoreString-Out-0 | out ICoreUInt8-Out-0 [1x31] entry 0 |
|---|---|---|
| 0 | u0 | [117, 48, 0, 0]… |
| 0.4 | u0 | [117, 48, 0, 0]… |
| 0.8 | u0 | [117, 48, 0, 0]… |
| 1.2 | u0 | [117, 48, 0, 0]… |
| 1.6 | u0 | [117, 48, 0, 0]… |
| 2 | u0 | [117, 48, 0, 0]… |
| 2.4 | u0 | [117, 48, 0, 0]… |
| 2.8 | u0 | [117, 48, 0, 0]… |
| 3.2 | u0 | [117, 48, 0, 0]… |
| 3.6 | u0 | [117, 48, 0, 0]… |
| 4 | u0 | [117, 48, 0, 0]… |
| 4.4 | u0 | [117, 48, 0, 0]… |
| 4.8 | u0 | [117, 48, 0, 0]… |
| 5.2 | u0 | [117, 48, 0, 0]… |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 117 … 117 |
ramp | Ramp: slope 1 from t = 0 | 117 … 117 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 117 … 117 |
step | Step: 0 -> 1 at t = 1 s | 117 … 117 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 6280f52f3 · produced by docsSample --out <folder> --blocks Rational_Resample,Three_Axis_Accelerometer,Three_Axis_Gyroscope,Three_Axis_Inertial_Measurement_Unit,Eclipse_Shadow_Model,To_String,String_To_ASCII,ASCII_To_String,Substring,String_Constant,String_Concatenate,String_Compare,String_Length --steps 60 · data docs/generated/samples/Control_Systems__Strings__String_To_ASCII.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).