ASCII To String — Control Systems/Strings
Control_Systems/Strings/ASCII_To_String · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
ASCII to String
Control Systems / Strings
Turns a vector of character codes into text: y = the characters with
codes u(1), u(2), …, up to the first 0. [104 105 0 0]
is "hi"; [104 0 105] is "h", because the first 0 ends the
text.
Ports
- Input – the codes u (
u8,ICoreUInt8), a row or a column of any length; one code is a one-character text. A matrix with more than one row and more than one column is refused, as it is in Simulink. - Output – the text y (
str,ICoreString), one value.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Codes are Latin-1 characters
A code from 1 to 127 is the ASCII character; a code from 128 to 255 is the Latin-1 character with that code – 233 is "é", 200 is "È" – exactly as in Simulink. Every code therefore makes exactly one character, so there is no code this block cannot turn into text.
The text stops at 255 bytes, a whole character at a time: a character from 128 to 255 takes two bytes, so at most 255 ASCII characters or 127 accented ones fit. Simulink has no such limit.
Code export
C, C++, Python, MATLAB, Java and Rust all write the same text for the same codes.
VHDL, Verilog and SystemVerilog do not carry text, and PLC Structured Text is not supported either: the language has a string type, but the check that runs an exported core cannot read one back. An export to any of these four stops and names this block and the reason.
Simulink bridge
Import and export, mapped to simulink/String/ASCII to String, which
has no parameters at all. Simulink's block takes only a uint8
input, so this block's input is uint8 too. The Simulink block has
no sampling-time setting of its own, so a positive Sampling Time (s)
stays on this side and is reported rather than written.
Notes
- Algebraic, with no state: the output depends only on the current input.
- String to ASCII is the inverse: its output fed back here gives the same text, for any text of Latin-1 characters that fits its width.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Strings/ASCII_To_String |
| family | Control_Systems/Strings |
| solver environment class | ICoreBlock_0_Control_Systems_1_Strings_2_ASCII_To_String |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/ASCII_To_String/ICoreBlock_0_Control_Systems_1_Strings_2_ASCII_To_String.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/ASCII_To_String/ICoreBlock_0_Control_Systems_1_Strings_2_ASCII_To_String.h |
| default size on canvas | 90 × 60 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreUInt8 | — |
| 2 | out | ICoreString | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/String/ASCII to String |
| port-count rule | PortsParam:: |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): codes are Latin-1 characters on both sides (measured: 200 is one
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
ASCII to String -- a vector of character codes in, text out y = the characters whose codes are u(1), u(2), ... up to (not including) the first 0. Each code is a Latin-1 character (see the header), written as one byte of UTF-8 below 128 and as two from 128 to 255. The text stops, a whole character at a time, at 255 bytes -- what the exported C buffer holds beside its terminator -- so every target cuts in the same place.
The output is a String signal, so the value leaves through the PORT (D2).
Sample results#
This block carries a ICoreString signal, whose value is text rather than a number and is not something a plot has an axis for. The samples are in the table below, exactly as the run recorded them.
| t | out ICoreString-Out-0 |
|---|---|
| 0 | |
| 0.4 | |
| 0.8 | |
| 1.2 | |
| 1.6 | |
| 2 | |
| 2.4 | |
| 2.8 | |
| 3.2 | |
| 3.6 | |
| 4 | |
| 4.4 | |
| 4.8 | |
| 5.2 |
Every 4th of 60 samples, from the step stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | — |
ramp | Ramp: slope 1 from t = 0 | — |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | — |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | — |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit 6280f52f3 · produced by docsSample --out <folder> --blocks Rational_Resample,Three_Axis_Accelerometer,Three_Axis_Gyroscope,Three_Axis_Inertial_Measurement_Unit,Eclipse_Shadow_Model,To_String,String_To_ASCII,ASCII_To_String,Substring,String_Constant,String_Concatenate,String_Compare,String_Length --steps 60 · data docs/generated/samples/Control_Systems__Strings__ASCII_To_String.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).