Sine Wave — Control Systems/Sources
Control_Systems/Sources/Sine_Wave · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Sine Wave
Control Systems / Sources
A source generating a sinusoid from the simulation clock:
y(t) = A·sin(ω·t + φ) + bias
Ports
- Output – the generated signal. It has no inputs.
Parameters
- Amplitude – the peak A.
- Frequency (Rad) – ω in radians per second, not Hz. For f hertz, enter 2πf.
- Phase Shift – φ in radians.
- Bias – a constant offset added to the wave.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It also sets how finely the wave is resolved, so a coarse rate visibly aliases a fast sinusoid.
Vector parameters
Any of the four may be a vector or matrix instead of a scalar: the others are then expanded to match, and the output takes that shape – one sinusoid per entry. Non-scalar parameters must agree in size, and the run stops with a message naming the block if they do not.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each uses a per-block local sample clock rather than a global one, and the four parameters are exposed as tunable parameters on the generated core. The three HDL targets carry the wave in simulation-only form: the sine is evaluated in real arithmetic and quantized on the way out to the fixed-point signal ports.
Simulink bridge
Import and export, mapped to simulink/Sources/Sine Wave.
"Amplitude" to Amplitude, "Frequency (Rad)" to
Frequency, "Phase Shift" to Phase, "Bias" to
Bias, "Sampling Time (s)" to SampleTime. Nothing is
left behind – every parameter has a counterpart, and Simulink's Frequency
is in radians per second too.
Notes
- Time-driven and stateless: the output depends only on the current time.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Sine_Wave |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Sine_Wave |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Sine_Wave/ICoreBlock_0_Control_Systems_1_Sources_2_Sine_Wave.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Sine_Wave/ICoreBlock_0_Control_Systems_1_Sources_2_Sine_Wave.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Amplitude | 1 | Amplitude |
Frequency (Rad) | 1 | Frequency |
Phase Shift | 0 | Phase |
Bias | 0 | Bias |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Sine Wave |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Amplitude | Amplitude | passes through |
Frequency (Rad) | Frequency | passes through |
Phase Shift | Phase | passes through |
Bias | Bias | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Sine_Wave.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).