Pulse Train — Control Systems/Sources
Control_Systems/Sources/Pulse_Train · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Pulse Train
Control Systems / Sources
A sum of shaped pulses placed at listed offsets – MATLAB's
pulstran:
y(t) = Σ ai · p(t − di)
The offsets and their amplitudes are a list, not a period, which is what separates this block from Pulse Generator: the pulses may be irregularly spaced, differently weighted, and of a shape other than rectangular. The train is finite – after the last pulse the output returns to zero and stays there.
Ports
- y – the train, in the amplitudes' own units. Scalar. The block takes no input: it is a source and reads only its own clock.
Parameters
- Pulse Offsets – where the pulses are, in seconds. Either a
vector of offsets, each pulse then having unit amplitude, or an
N×2 matrix whose first column is the offset and whose second is the
amplitude – the two shapes MATLAB's
Dargument accepts. [1 1; 2 −0.6; 3 0.8] by default: three pulses, the middle one inverted and the last one smaller. - Pulse Shape – which pulse is placed at each offset:
- Rectangular –
rectpuls: 1 across the width, 0 outside it. ⚠ The leading edge is included and the trailing one is not, which is MATLAB's own asymmetry rather than a rounding here. - Triangular –
tripuls: rises to 1 at the apex and falls back, the apex placed by Triangular Skew. - Gaussian RF –
gauspuls: a cosine at Center Frequency (Hz) under a Gaussian envelope whose width follows from Fractional Bandwidth. Unlike the other two it has no edges, so it never reaches exactly zero.
- Rectangular –
- Pulse Width (s) – the full width of a Rectangular or Triangular pulse. 0.5 by default. Ignored by Gaussian RF, whose width comes from its bandwidth instead.
- Triangular Skew – where the apex sits, from −1 (at the leading edge) through 0 (centred) to +1 (at the trailing edge). 0 by default. Read only by Triangular.
- Center Frequency (Hz) – the cosine carried under the Gaussian envelope. 5 by default. Read only by Gaussian RF.
- Fractional Bandwidth – the envelope's width, as a fraction of the centre frequency, at the −6 dB reference MATLAB uses by default. 0.5 by default; larger is a shorter pulse. Read only by Gaussian RF.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.
Every offset, amplitude and derived coefficient is structural and is inlined into the arithmetic at export time rather than exposed as a tunable parameter: they decide the shape of the signal rather than scaling it, and a core with a different offset list is a different signal. Re-export after changing any of them.
⚠ The three HDL targets are simulation-only, as every source in
this library is: they read the testbench's own simulation time rather than
counting their own samples, and carry the arithmetic in real,
quantising only at the port boundary.
⚠ A pulse edge placed exactly on a sample can differ in the HDL targets. The rectangular pulse's edge test is exact, and the three HDL targets compute time as a real number supplied by the testbench rather than as an exact multiple of the period – so a sample sitting exactly on a leading edge may fall on the other side of it there. Place edges between samples if that matters; the default offsets do.
Simulink bridge
No equivalent (Support::None). Measured rather than
assumed: a find_system sweep at depth 6 under masks over 22 DSP
System Toolbox libraries plus simulink and
simulink_extras on R2026a matches nothing for pulse train or
pulstran. Simulink's own Pulse Generator is a different block and
is already bridged by Control_Systems/Sources/Pulse_Generator: its
pulses are rectangular, identical and periodic, so a mapping onto it would drop
the offset list that makes this block what it is. The bridge reports this block
rather than dropping it silently, and it therefore has no parity
testbench. Code export verification still covers it across all ten
languages.
Notes
- Stateless, and a pure function of time: the output at a sample depends on nothing but the clock, so the block carries no state in any of the ten targets and needs no initial condition.
- No state space. The block is not linear in an input – it has no input – so it carries none and model reduction correctly declines to merge it.
- Rectangular and Triangular are bit-exact against MATLAB R2026a and
Gaussian RF agrees to one unit in the last place, measured over 60
samples of a four-pulse train. The last is a library difference in
expandcosrather than a difference in the formula. - ⚠ The triangular apex is its own case, and it is reachable. With a skew of 0 the apex sits exactly at the offset, which every offset that is a whole number of sample periods hits – so the branch runs rather than sitting there for completeness.
- Pulses may overlap, and where they do the amplitudes add. Nothing clips.
- Compare with Pulse Generator for a regular rectangular train, and with Repeating Sequence Stair for an arbitrary waveform given sample by sample.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Pulse_Train |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Pulse_Train |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Pulse_Train/ICoreBlock_0_Control_Systems_1_Sources_2_Pulse_Train.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Pulse_Train/ICoreBlock_0_Control_Systems_1_Sources_2_Pulse_Train.h |
| default size on canvas | 96 × 72 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Pulse Offsets | [1 1; 2 -0.6; 3 0.8] | — |
Pulse Shape | Rectangular%~%Triangular%~%Gaussian RF~~Rectangular | — |
Pulse Width (s) | 0.5 | — |
Triangular Skew | 0 | — |
Center Frequency (Hz) | 5 | — |
Fractional Bandwidth | 0.5 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): no Simulink equivalent: pulstran is a Signal Processing Toolbox function and that toolbox ships no Simulink library. Measured 2026-09-10 on R2026a -- a find_system sweep at depth 6 under masks over 22 DSP System Toolbox libraries plus simulink and simulink_extras matches nothing for pulse train or pulstran. Simulink's own Pulse Generator is a different block, already bridged by Control_Systems/Sources/Pulse_Generator: its pulses are rectangular, identical and periodic, so a mapping onto it would silently drop the offset list. Reported rather than dropped, and it carries no parity testbench
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Pulse Train -- a sum of shaped pulses placed at listed offsets y(t) = SUM over i of a_i * p(t - d_i), which is MATLAB's
pulstran. The three shapes are transcribed fromrectpuls.m,tripuls.mandgauspuls.mrather than from the doc pages, and the emitted bodies keep MATLAB's own spelling of each formula for the reason the header banner gives: an algebraically equal rearrangement costs bit-exactness.ONE DESCRIPTION OF THE ARITHMETIC, TEN TARGETS. Everything below
Spellis written once and spelled per language, exactly as the Pulse Metrics family does for its tracker: two copies of a formula are two chances to drift, and code export verification would report the drift as a code-generation fault in whichever backend happened to be wrong.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit 647426467 · produced by docsSample --out <folder> --blocks Pulse_Train --steps 60 · data docs/generated/samples/Control_Systems__Sources__Pulse_Train.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).