Ground — Control Systems/Sources
Control_Systems/Sources/Ground · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Ground
Control Systems / Sources
A source that emits zero for the whole run:
y = 0
Its purpose is to terminate an input that has nothing to drive it, so a model can be built and run with part of it not yet wired.
Ports
- Output – the zero signal. It has no inputs, and its size is the
Output Size parameter:
[1 1]gives a scalar,[3 1]a 3×1 column,[2 3]a 2×3 matrix. Every entry is zero.
Parameters
- Output Size – the output's shape, as a two-entry list
[rows cols](either orientation is accepted). Both entries must be whole numbers of at least 1. The default[1 1]is a scalar zero, which is what Simulink's Ground produces. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. The value emitted never changes, so the rate only decides how often the port is refreshed.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is exposed as a tunable parameter – unlike Constant, whose whole content is a retunable value, a ground has nothing to retune, so every target emits a zero literal directly. Like Constant and unlike every time-driven source in this family, the block reads no clock, so the three HDL targets are genuinely synthesizable rather than simulation-only.
Simulink bridge
Import and export, mapped to simulink/Sources/Ground. Simulink's Ground has
no parameters at all, so nothing crosses in either direction – including
the rate. "Sampling Time (s)" does NOT cross: the global
"Sampling Time (s)" → SampleTime pair that every other block enjoys
is suppressed for this one, because setting a parameter a Simulink block does not
define is a hard error that aborts the whole generated script. A Ground given an
explicit positive rate here reports that the rate stayed on the ICore side.
"Output Size" does not cross either, and cannot: Simulink's Ground has no width
parameter because a Simulink line negotiates its width between both ends, while an
ICore signal takes its size from its source. An exported Ground therefore adapts to
whatever it is wired to on the Simulink side, and an imported one comes back as the
default scalar.
Notes
- Algebraic, stateless and time-independent: the output is zero at every instant, so nothing about it changes if the solver's rate or start time does.
- A Ground wired into a port that expects a different size is a size disagreement reported by the receiving block, not by this one. Set Output Size to the shape that port expects.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Ground |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Ground |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Ground/ICoreBlock_0_Control_Systems_1_Sources_2_Ground.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Ground/ICoreBlock_0_Control_Systems_1_Sources_2_Ground.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Output Size | [1 1] | not crossed |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Ground |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| deliberately not crossed | Output Size |
Caveat (shown to the user): Simulink's Ground has NO dialog parameters, verified against the block itself: get_param(...,'DialogParameters') on it returns an empty struct. That includes SampleTime, so this entry sets hasSampleTimeParam=false and the rate stays on the ICore side -- emitting the standard set_param would be a hard MATLAB error that aborts the whole generated script. 'Output Size' has no counterpart either: a Simulink line negotiates its width between both ends, so its Ground adapts to whatever it terminates, while an ICore signal takes its size from its source and this block has to be told.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Ground block — y = 0, a signal that is identically zero The zero source. Simulink's Ground exists to terminate an unconnected INPUT port, and takes its width from whatever it is wired to, because a Simulink line negotiates its width between both ends. ICore does not work that way: a signal's size is announced by its SOURCE, and this block is the source. So the one thing this block carries that Simulink's does not is an "Output Size" — without it a Ground could only ever feed a scalar port, which is the one place a zero terminator is least useful.
That asymmetry is the block's only subtlety. Everything else is as small as a block gets: no state, no clock, no arithmetic, and nothing on the params object — zero needs no parameter to carry it, so unlike Constant (whose whole content is a tunable value) this block emits literals.
Code export: all ten targets, and the three HDL ones are genuinely synthesizable rather than simulation-only — like Constant and unlike every time-driven source in this family, nothing here reads the clock.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Ground.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).