Counter Limited — Control Systems/Sources
Control_Systems/Sources/Counter_Limited · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Counter Limited
Control Systems / Sources
A sample counter that wraps at a limit of your choosing:
y[k] = k mod (limit + 1), one step per sample
It emits 0 on the first sample, one more on each sample after it, up to and including the configured limit, then starts again from 0.
Ports
- Output – the current count, always a scalar. It has no inputs; the count comes from the block's own state, advancing once per sample.
Parameters
- Upper Limit – the highest value emitted, and it IS emitted: a limit of 5 produces 0,1,2,3,4,5,0,... so the cycle is limit+1 samples long. A whole number of zero or more (zero gives a counter permanently at 0); a value outside that stops the run with a message naming the block.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. On this block it also sets how fast the count advances, since one sample is one increment.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The wrap length is baked into the arithmetic at export time rather than exposed as a tunable parameter: it is structural, and a counter whose cycle could be changed on a built core would be a different block. Alone among the sources this block and Counter Free-Running read no clock at all – they count their own invocations – so the three HDL targets are not simulation-only here; they are an ordinary counting register.
The HDL caveat is range rather than timing. A signal is carried in Q16.16 there, which reaches 32767, so a limit above that produces counts the HDL signal cannot represent even though the software targets carry them without trouble. Keep Upper Limit at 32767 or below for a model intended for the HDL backends.
Simulink bridge
Import and export, mapped to simulink/Sources/Counter Limited.
"Upper Limit" to uplimit, with the same inclusive meaning on both
sides. The rate crosses too, but under Simulink's own name for it: this block is a
masked subsystem there, and it calls its rate parameter tsamp rather
than SampleTime – so "Sampling Time (s)" maps to
tsamp, exactly as Tapped Delay does for the same reason.
Notes
- Stateful: the whole state is the count, which starts at 0 at the beginning of every run, so a re-run reproduces the sequence exactly.
- Discrete by nature, so it always takes its period from its own "Sampling Time (s)".
- The count is driven by SAMPLES, not by elapsed time. Changing the rate changes how quickly the counter climbs in wall-clock terms but not the sequence of values it produces.
- See Counter Free-Running for the same counter wrapping at a register width instead – that block's limit is 2bits−1, this one's is whatever you say.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Counter_Limited |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Counter_Limited |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Counter_Limited/ICoreBlock_0_Control_Systems_1_Sources_2_Counter_Limited.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Counter_Limited/ICoreBlock_0_Control_Systems_1_Sources_2_Counter_Limited.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Upper Limit | 7 | uplimit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Counter Limited |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| rate parameter name | tsamp |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Upper Limit | uplimit | passes through |
Caveat (shown to the user): the rate crosses as 'tsamp' - Simulink's Counter Limited is a masked subsystem and does not use the standard 'SampleTime' parameter name
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Counter Limited block — y[k] = k mod (limit + 1) A sample counter that wraps at an arbitrary upper limit rather than at a power of two. It emits 0 on the first sample and one more on each sample after it, up to and INCLUDING the configured limit, then starts again from 0:
y[k] = k mod (limit + 1) k = 0, 1, 2, ... one per SAMPLE
Verified against simulink/Sources/Counter Limited: with uplimit = 5 that block emits 0,1,2,3,4,5,0,1,... beginning at t = 0, which is what this one does. Note the inclusive limit -- the cycle is limit+1 samples long, not limit -- which is the one thing to get right here and the reason modulus() exists rather than each generator adding the 1 itself.
Discrete by nature (setDiscreteOnlyBlock): the count advances once per SAMPLE, so the block must take its period from its own "Sampling Time (s)" rather than be pushed through a continuous solver's intermediate stages, which would advance it several times per step.
Code export: all ten targets, none of them simulation-only -- the block reads no clock, so the HDL cores are an ordinary counting register. The one HDL caveat is RANGE, not timing: a signal is Q16.16 there, so limits above 32767 do not fit. See the description.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Counter_Limited.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).