Clock — Control Systems/Sources
Control_Systems/Sources/Clock · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Clock
Control Systems / Sources
A source that outputs the current simulation time:
y(t) = t
Ports
- Output – the current time in seconds, always a scalar. It has no inputs; the value comes from the solver's clock, so it begins at the model's start time rather than always at zero.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the only parameter this block has: there is nothing to configure about reporting the time, and the rate decides only how often the port is refreshed, not what the value means.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. Each uses a per-block local sample clock – the
model's start time plus tick times sampling time – rather than a global one,
which is the same convention Step, Sine Wave and Chirp Signal follow. Nothing is
exposed as a tunable parameter, because the block has no configuration to tune.
The three HDL targets are simulation-only: they read the testbench-driven
sim_time real, and a synthesized core has no simulation time to
read.
Simulink bridge
Import and export, mapped to simulink/Sources/Clock. There are no
parameter pairs to list – this block has no configuration, and Simulink's
Clock exposes only DisplayTime and Decimation, which
control how the block face draws itself and how often that drawing refreshes.
Neither changes the signal, so neither has an ICore counterpart.
Simulink's Clock has no SampleTime parameter, so
"Sampling Time (s)" does not cross – the exported block runs at the
surrounding Simulink rate. That is a genuine difference from most of the library,
where the rate is mapped globally.
Notes
- Time-driven and stateless: the output depends only on the current time, and a re-run reproduces it exactly.
- Continuous by nature. Under a continuous solver the block is evaluated at the solver's intermediate stages too, and reports each of those instants faithfully. Use Digital Clock for the quantized form – the time of the last sample hit – which is what a discrete controller actually sees.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Clock |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Clock |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Clock/ICoreBlock_0_Control_Systems_1_Sources_2_Clock.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Clock/ICoreBlock_0_Control_Systems_1_Sources_2_Clock.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Clock |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross. Simulink's DisplayTime and Decimation affect only how the block face draws itself, so they have no ICore counterpart
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Clock block — y = t, the current simulation time A source with no configuration at all: it reports the solver's clock. Its whole reason to exist is to make time available to the arithmetic in a diagram — a ramp, a schedule, a time-varying gain — without every such block having to grow a clock of its own.
It is the CONTINUOUS clock: it reports whatever instant it is asked about, unquantized. Its companion Digital Clock reports the time of the last sample hit instead, which is the same number whenever the two run at the same rate and a staircase whenever they do not.
Code export: all ten targets. Each carries a per-block local clock — start time plus tick times sampling time — rather than a global one, so the block reads the same instant the live solver hands compute_h. The three HDL targets take it from the testbench-driven
sim_timereal, which makes them SIMULATION-ONLY: a synthesized core has no notion of simulation time.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Clock.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).