Band Limited White Noise — Control Systems/Sources
Control_Systems/Sources/Band_Limited_White_Noise · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Band-Limited White Noise
Control Systems / Sources
A source producing normally distributed noise, band-limited by holding each draw for one noise period:
y = σ·g[k], where σ = √(power / Tn) and g[k] is a fresh standard-normal draw every Tn seconds
True white noise has infinite variance, so what is actually generated is a sequence of normal draws held across a sample period. The holding is what limits the bandwidth, and it is why the requested power spectral density becomes that per-sample standard deviation.
Ports
- Output – the noise signal, always a scalar. It has no inputs; the sequence comes from the block's own generator and seed.
Parameters
- Noise Power – the height of the power spectral density, not a standard deviation. It reaches the output through σ above, so halving the noise sample time raises the amplitude by √2 for an unchanged power. Must be zero or more.
- Noise Sample Time (s) – Tn, how often a new value is drawn. Anything coarser than the block's own rate is held for round(Tn / sampling time) samples, which is where the band limiting comes from; anything at or below it draws afresh every sample. Must be greater than zero.
- Seed – the generator's starting state. The same seed always produces the same sequence, so a run is reproducible and two blocks with different seeds are independent. Any whole number.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is separate from the noise sample time above: this is how often the block runs, that is how often it draws. The two being separate is what lets a noise source be genuinely slower than the model it feeds.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, and every one of them produces the identical sequence – the generator is a 32-bit linear congruential generator feeding a sum of twelve uniforms, which uses only integer arithmetic and addition and so needs no agreement between platform maths libraries. σ is exposed as a tunable parameter; the seed and the hold length are baked in at export time, being structural. The three HDL targets are simulation-only: they carry the generator in real arithmetic, because the 32-bit generator state does not fit in the Q16.16 datapath at all.
Simulink bridge
Neither direction. Simulink has a counterpart –
simulink/Sources/Band-Limited White Noise, whose Cov,
Ts and seed line up one for one with the three
parameters above – but its sequence comes from Simulink's own random
number generator and cannot be reproduced by generated code. An exported model
would therefore be statistically identical and sample-wise different, which no
parity test could confirm and no user could rely on. Rather than assert a mapping
that nothing verifies, the bridge reports this block and skips it. To cross a
model containing one, place the Simulink block by hand and copy the three values
across: the meanings match exactly, and only the stream will differ.
Notes
- Stateful: the generator state, the countdown to the next draw and the held value. All three are reset at the start of every run, so a re-run reproduces the sequence exactly, as does a freshly exported core.
- Discrete by nature, so it always takes its period from its own "Sampling Time (s)".
- The draw is a sum of twelve uniforms rather than a Box-Muller transform. That is an exact standard normal in mean and variance, and indistinguishable from one for control work, but it has no tails beyond ±6σ – worth knowing if the model under test is specifically about rare large excursions.
- Two blocks in one model with the same Seed produce the same sequence and are therefore perfectly correlated. Give them different seeds.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Band_Limited_White_Noise |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Band_Limited_White_Noise |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Band_Limited_White_Noise/ICoreBlock_0_Control_Systems_1_Sources_2_Band_Limited_White_Noise.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Band_Limited_White_Noise/ICoreBlock_0_Control_Systems_1_Sources_2_Band_Limited_White_Noise.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Noise Power | 0.1 | — |
Noise Sample Time (s) | 0.1 | — |
Seed | 23341 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Band-Limited White Noise matches this block parameter for parameter (Cov, Ts, seed) but not SAMPLE for sample: its sequence comes from Simulink's own random number generator, which generated code cannot reproduce. An exchanged model would be statistically identical and numerically different, and no parity test could confirm it - so the mapping is reported here rather than asserted. Place the Simulink block by hand and copy the three values across if you need it
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Band-Limited White Noise block — a normally distributed sample held for the noise period y(t) = sigma * g[k] held constant across each noise period sigma = sqrt(power / Ts_noise)
White noise in continuous time has infinite variance, so what every tool actually provides is a sequence of normal draws HELD across a sample period: holding is what band-limits it, and the power spectral density the user asks for becomes a per-sample standard deviation of sqrt(power / Ts_noise). Verified against simulink/Sources/Band-Limited White Noise, whose output has exactly that standard deviation at four different (Cov, Ts) pairs.
WHY THE GENERATOR IS WRITTEN BY HAND. Code-export verification compares each of the ten generated cores against this C++ one SAMPLE BY SAMPLE, so a noise source has to produce the identical stream in ten languages or fail its whole row. That rules out every language's own RNG, and it also rules out Box-Muller, whose log and cos agree only to within each platform's libm. What is left is a 32-bit LCG feeding an Irwin-Hall sum -- integer arithmetic and addition, nothing else -- which is bit-identical everywhere including the five backends that have no unsigned integer type at all. See the header for why the intermediates stay exact in a double.
WHY THERE IS NO SIMULINK BRIDGE. The parameters correspond one for one (Cov, Ts, seed), but the STREAM cannot: Simulink's noise comes from its own generator, so an exported model would be statistically identical and sample-wise different, and no parity testbench could ever pass. Registering the block as exportable would assert a mapping that nothing checks, so it registers Support::None with that reason and the bridge reports it rather than emitting something that quietly disagrees. See the description.
Code export: all ten targets. The three HDL ones are SIMULATION-ONLY -- they carry the generator in real arithmetic, because a Q16.16 datapath cannot hold the 32-bit LCG state at all, let alone advance it.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Band_Limited_White_Noise.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).