Terminator — Control Systems/Sinks
Control_Systems/Sinks/Terminator · 1 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Terminator
Control Systems / Sinks
Accepts whatever reaches it and discards it. The block computes nothing and produces nothing: it exists so an output port the model deliberately does not use has somewhere to go, and so a reader of the diagram can tell a signal that is unused on purpose from one that was forgotten.
Ports
- Input – the signal to discard, of any size [m,n]. It is never read.
- No outputs – the Terminator is a pure sink.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. Nothing observable depends on it, since the block produces no value at any rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each emits a named body that does nothing, which is exactly what the block does. It is emitted rather than left out so the block keeps its place in the generated execution order – a missing entry there reads as a block that got lost on the way out.
Simulink bridge
Import and export, mapped to simulink/Sinks/Terminator. There are no
parameters to carry on either side. Simulink's Terminator has no
SampleTime parameter, so "Sampling Time (s)" does not cross;
the block simply runs at the surrounding Simulink rate. The
Commonly Used Blocks copy of the same block resolves to this one on
import.
Notes
- Algebraic, with no state, and it never reads its input – connecting a signal to a Terminator cannot change what that signal is.
- To keep a signal's values rather than throw them away, use the Signal Recorder (into the variables space), To File (onto disk) or the Scope (onto a chart).
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sinks/Terminator |
| family | Control_Systems/Sinks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sinks_2_Terminator |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Terminator/ICoreBlock_0_Control_Systems_1_Sinks_2_Terminator.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Terminator/ICoreBlock_0_Control_Systems_1_Sinks_2_Terminator.h |
| default size on canvas | 50 × 50 px |
| ports at insert | 1 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sinks/Terminator |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 1 port (1 in, 0 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Terminator block -- accepts a signal and discards it No math, no state, no outputs. The block exists so that an output port a model deliberately does not use has somewhere to go, and so the diagram says "unused on purpose" rather than leaving a reader to guess.
Code export: a named do-nothing body per target. Emitted rather than skipped -- an empty generator string fails the whole export for that language.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-In-0 |
|---|---|---|
| 0 | 0 | 0 |
| 0.4 | 0 | 0 |
| 0.8 | 0 | 0 |
| 1.2 | 1 | 1 |
| 1.6 | 1 | 1 |
| 2 | 1 | 1 |
| 2.4 | 1 | 1 |
| 2.8 | 1 | 1 |
| 3.2 | 1 | 1 |
| 3.6 | 1 | 1 |
| 4 | 1 | 1 |
| 4.4 | 1 | 1 |
| 4.8 | 1 | 1 |
| 5.2 | 1 | 1 |
Every 4th of 60 samples, from the step stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category sink · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sinks__Terminator.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).