Generated reference › Record — Control Systems/Sinks
kind: generated#block#control-systems-sinks

Record — Control Systems/Sinks

Control_Systems/Sinks/Record · 1 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Record

Control Systems / Sinks

Plots what it receives and keeps it: the traces are drawn live on the chart attached to the block, and the same samples are saved into the variables space as time series, so a run's data outlives the run it was watched in. One trace and one variable per scalar channel – a [3,1] input draws three lines and saves three series.

Ports

  • Inputs – one by default, and the count is user-editable. Any signal size is accepted.
  • No outputs – Record is a pure sink and passes nothing on.

Channels

One variable per scalar channel, in port and element order. A single channel takes the configured name exactly as typed; several take name_0, name_1, and so on – the same naming the Signal Recorder uses.

Parameters

  • Variable Name – the name to record under. This names something the block creates, so it is not looked up in the variables space; an existing variable of that name is overwritten at the end of the run.
  • Max Samples – memory cap on the recording. Once reached, the most recent samples are kept and the oldest are dropped. Simulink's counterpart defaults to inf; a finite cap is kept here because a recorded series is stored in the project.
  • Decimation – keep every Nth sample. 1 keeps every sample. It gates the plot and the recording together, which is the difference between this block and a Scope wired beside a Signal Recorder: what you see is exactly what was kept.
  • Sampling Time (s) – how often a sample is taken. Zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text – but no target has a chart or a variables space, so each records the way that target can be read back. The nine console targets stream one channel,time,value line per retained sample, so the run's transcript is a CSV of exactly the samples the in-app block would have kept and drawn, with identical channel names, channel order and decimation. PLC Structured Text instead owns one ring buffer per channel, sized to "Max Samples" – making ST the one target that reproduces the most-recent-N truncation exactly, and leaving the recording observable from an HMI or trace.

Simulink bridge

Import and export, mapped to simulink/Sinks/Record. "Variable Name" to VariableName, "Max Samples" to MaxDataPoints, "Decimation" to Decimation. "Sampling Time (s)" does NOT cross – Simulink's Record block defines no SampleTime parameter at all, and writing one is a hard error that aborts the whole generated script, so the rate stays on the ICore side and a Record configured with an explicit rate reports that it did not cross. The port count has no parameter behind it either: Simulink derives it from the block's own port configuration rather than from a settable number, so a multi-input Record must be widened on the far side.

Notes

  • The recording is handed over when the run finishes, not while it runs; the traces, by contrast, are drawn live.
  • The traces are cleared at the start of every run. The recorded variables are not – they are ordinary variables, and the previous run's are overwritten only when this run finishes.
  • On an infinite simulation the chart streams a rolling window while the recording still honours "Max Samples".

Code facts#

FactValue
registered typeControl_Systems/Sinks/Record
familyControl_Systems/Sinks
solver environment classICoreBlock_0_Control_Systems_1_Sinks_2_Record
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Record/ICoreBlock_0_Control_Systems_1_Sinks_2_Record.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Record/ICoreBlock_0_Control_Systems_1_Sinks_2_Record.h
default size on canvas80 × 70 px
ports at insert1 in, 0 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDouble

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Variable Namerecordout
Max Samplesstd::to_string(FALLBACK_MAX_SAMPLES)
Decimation1

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::Both
Simulink pathsimulink/Sinks/Record
port-count rulePortsParam::None
SampleTime parameterno — the counterpart defines none; the rate stays on the ICore side
ICore configSimulink parameterValue translation
CONFIG_VARIABLE_NAME.c_str()VariableNamepasses through
CONFIG_MAX_SAMPLES.c_str()MaxDataPointspasses through
CONFIG_DECIMATION.c_str()Decimationpasses through

Caveat (shown to the user): the port count does not cross: Simulink's Record derives it from its own port configuration rather than from a settable parameter, so a multi-input Record must be widened on the far side

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

  • B0 Ports lists 2 entries for 1 port (1 in, 0 out) — grouped, or one undocumented? a reader must say
  • B0 3 Simulink params rule(s) this tool cannot resolve

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

Sample results#

tin ICoreDouble-Out-0out ICoreDouble-In-0
000
0.400
0.800
1.211
1.611
211
2.411
2.811
3.211
3.611
411
4.411
4.811
5.211

Every 4th of 60 samples, from the step stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0 … 1
rampRamp: slope 1 from t = 00 … 5.8
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias-1 … 0.9996
tableRepeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample-2 … 3

Plotted: step — Step: 0 -> 1 at t = 1 s

Category sink · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sinks__Record.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).