Out Bus Element — Control Systems/Sinks

Out Bus Element

Control Systems / Sinks

Packs several named signals into one wider signal, so a subsystem can leave through a single port carrying all of them. y is the vertical stack of the inputs in port order – a [2,1] and a [3,1] element become one [5,1] bus – and each input's description label is the name of the element it contributes.

Ports

• Inputs – the bus elements, two by default and the count is user-editable. At least one is required. They may differ in row count but must all agree in column count, since the stack is vertical. The description label of each input is that element's NAME – it carries meaning here, it is not decoration, and it is what the generated code and the run messages call the element.
• Output – the bus: as many rows as all elements together, and the elements' shared column count. Wire it into a Subsystem Output Gate to send the whole bus out of the subsystem.

Elements

Element k occupies the rows its input contributed, in port order: the first input owns rows 0 upward, the second continues from there. An input whose description label is left empty is named element_k by position, so a partly-labelled block still works and still reads.

Parameters

• Port Name – the bus's own name, used to qualify the elements (OutBus.err) in generated code comments and run messages. It names something this block creates, so it is not looked up in the variables space.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The stack is unrolled at export time, so the generated code is plain assignment with no loop over ports, and each element's rows carry a comment naming the element they came from – which is the only thing a bus is once the types are gone.

Simulink bridge

No equivalent, and deliberately so. Simulink's Out Bus Element carries exactly ONE element per block – its Element parameter – and several blocks sharing a PortName add up to one bus. One block here is therefore N blocks there, and the block catalog maps one type to one type; registering the mapping anyway would export a bus of five elements as its first element and lose the other four silently. Build the far side as N Out Bus Element blocks sharing a port name, or export the bus as a plain Mux into an Outport, which does cross.

Notes

• Algebraic, with no state – pure signal routing. Nothing is scaled, reordered or renamed on the way through; only the layout changes.
• Not a sink, despite the family: it has an output, and it is code-export verified like any other block that produces one.
• The output size is derived from the inputs, so it is only settled once the upstream blocks have resolved theirs.