Zero Phase Filter — Control Systems/Signal Smoothing
Control_Systems/Signal_Smoothing/Zero_Phase_Filter · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Zero Phase Filter
Control Systems / Signal Smoothing
Filters the last W samples forwards and then backwards, so the filter's phase response cancels itself and nothing in the output is shifted in time:
y = filtfilt(b, a, u), read at the centre of the window
This is MATLAB's filtfilt. A zero-phase filter is
acausal – it needs samples from both sides of the one it answers
– so a streaming block has to buy that with delay: the output lags the
input by (W−1)/2 samples, and in exchange nothing is phase
distorted.
Ports
- u – the signal to filter. Scalar: one channel and its own window – see Notes.
- y – the zero-phase filtered value at the centre of that window. Scalar.
Parameters
- Window Length – W, how many samples the filter sees. An
odd whole number from 5 to 101 – odd because the answer is the
centre sample and an even window has none. It must also be more than
3·(n−1), where n is the longer of the two coefficient
vectors, which is the record length
filtfiltitself demands. Bounded above because the dot product is unrolled at export. - Numerator – b, the filter's numerator coefficients, a vector of up to 12 entries in the usual descending order (b₀ first).
- Denominator – a, the denominator, likewise. Its first entry must be non-zero; everything is normalised by it, exactly as MATLAB does. Use [1] for an FIR filter.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.
No filter runs in any exported core, in either direction.
filtfilt is linear in the window – the passes, the
reversal, the end extension and the initial conditions are all linear maps –
so the centre sample is a fixed linear functional of the W samples, and
the block solves for that functional once when the configuration loads. What a
core carries is W numbers and one multiply-accumulate over a shift
register. The bank is structural: it follows from the window length and
both coefficient vectors together, so re-export after changing any of them.
The three HDL targets are genuine synthesizable Q16.16: a shift register and one fixed multiply-accumulate, with the products accumulated at full width and shifted back once.
Simulink bridge
None (Support::None). filtfilt is a Signal
Processing Toolbox function and that toolbox ships no Simulink library, so
there is no path a diagram could name. The bridge reports this block rather than
dropping it silently, and it therefore has no parity testbench; code
export verification still covers it across all ten languages.
Notes
- Stateful, and discrete by nature
(
setDiscreteOnlyBlock(true)): the window advances once per sample. - ⚠ The filter you get is the SQUARE of the filter you designed. The
data passes through H twice, so the magnitude response is
|H|²: a design with a −3 dB corner has a −6 dB corner
here, and its transition band is twice as steep. That is
filtfilt's behaviour rather than this block's, and it is the thing most often got wrong – design for half the attenuation you want. - ⚠ It lags, and it must. A zero-phase filter needs samples on both sides of the one it answers, so the centre of the window is the newest sample it can answer for: the output is (W−1)/2 samples behind the input. Savitzky-Golay Filter makes the same trade for the same reason. If the delay is what matters and the phase is not, an ordinary Discrete Filter is the block to reach for.
- ⚠ The bank is not exactly symmetric, and symmetrising it would be
wrong.
filtfiltextends the record by 3·(n−1) samples of odd reflection at each end and seeds each pass with steady-state initial conditions, and those two are not mirror images of one another over a finite window. Measured at W = 15 with b = [0.2 0.3 0.2], a = [1 −0.4 0.15], the taps either side of the centre are 0.22051553798359172 and 0.22051735331508093 – equal to six digits and no further. - Verified against MATLAB. At those settings the bank reproduces
R2026a's own
filtfiltcentre row to 5.6e−17, one unit in the last place, and applied to a fifteen-sample window it answers 0.4657953074281756 against MATLAB's 0.46579530742817565. - ⚠ Not every (b, a) is a filter this block can build a bank for. A denominator whose steady-state system is singular has no initial conditions to seed with; that is detected when the configuration loads and reported with a reason, rather than emitting the arbitrary answer a pseudo-inverse would produce.
- The window is zero-prefilled, so the first W−1 outputs of a run are a startup transient – the convention Detrend, Savitzky-Golay Filter and Polynomial Fit all follow.
- Scalar only. One channel and its own history; wire one block per channel.
- No state space. Linear in the input, but through a fixed filter bank over W past samples rather than an A/B/C/D pair, so model reduction correctly declines to merge it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Smoothing/Zero_Phase_Filter |
| family | Control_Systems/Signal_Smoothing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Smoothing_2_Zero_Phase_Filter |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Smoothing/Zero_Phase_Filter/ICoreBlock_0_Control_Systems_1_Signal_Smoothing_2_Zero_Phase_Filter.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Smoothing/Zero_Phase_Filter/ICoreBlock_0_Control_Systems_1_Signal_Smoothing_2_Zero_Phase_Filter.h |
| default size on canvas | 134 × 72 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Window Length | 15 | — |
Numerator | [0.2 0.3 0.2] | — |
Denominator | [1 -0.4 0.15] | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): filtfilt is a Signal Processing Toolbox function, not a Simulink library block -- that toolbox ships no Simulink library at all -- so there is no path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Zero Phase Filter -- MATLAB's filtfilt(b, a, x) over a running window Forward, reverse, forward, reverse: the filter's phase response cancels itself, so the output is not shifted in time relative to the input. That is acausal, and a stream has no future, so the block runs filtfilt over the last W samples and publishes the value at the CENTRE -- a lag of (W-1)/2 samples, the same trade Savitzky_Golay_Filter makes in its centred mode.
ONE SOLVE, THEN ARITHMETIC. filtfilt is LINEAR in the window: the forward pass, the reversal, MATLAB's odd end-extension and its steady-state initial conditions are every one of them linear maps, so the centre sample is a fixed linear functional of the W samples. The bank is built once per configuration load by running this file's own filtfilt over the W unit vectors and keeping the centre row, and every generated core carries W numbers and one multiply-accumulate. NO FILTER RUNS IN ANY EXPORTED CORE, in either direction.
TRANSCRIBED FROM MATLAB'S ALGORITHM AND THEN MEASURED AGAINST IT.
filtfiltpads the record with nfact = 3*(n-1) samples of ODD REFLECTION at each end (2*x(1) - x(nfact+1:-1:2), and the mirror at the far end), seeds each pass with zi*y(1) where zi solves (I - Z) zi = b(2:n) - b(1)*a(2:n), filters, reverses, filters, reverses, and trims. At W = 15 with b = [0.2 0.3 0.2] and a = [1 -0.4 0.15] the bank this file builds reproduces R2026a's own filtfilt centre row to 5.6e-17 -- one unit in the last place -- and applied to the fifteen-sample windoww = [1.2 0.7 2.5 0.3 0.12 0.8 1.1 -0.22 0.45 1.7 0.35 0.62 0.09 -1.4 0.66]
it answers 0.4657953074281756 against MATLAB's 0.46579530742817565.
⚠ THE BANK IS NOT EXACTLY SYMMETRIC and that is the edge handling, not a defect: at those settings the taps either side of the centre are 0.22051553798359172 and 0.22051735331508093, equal to six digits and no further. A reader who "fixes" that by symmetrising the bank is no longer computing filtfilt.
⚠ AND THE FILTER A USER GETS IS THE SQUARE OF THE ONE THEY DESIGNED: two passes give |H|^2, so a -3 dB corner becomes -6 dB. That is filtfilt's behaviour and the description says so.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.01235 … 0.294 |
ramp | Ramp: slope 1 from t = 0 | -0.003504 … 4.443 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.8562 … 0.8592 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.8713 … 1.366 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit 29032ce504d54aa5c75816c5fa5e85450aab1e4d · produced by docsSample --out <folder> --blocks Zero_Phase_Filter --steps 60 · data docs/generated/samples/Control_Systems__Signal_Smoothing__Zero_Phase_Filter.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).