Variant Source — Control Systems/Signal Routing

Variant Source

Control Systems / Signal Routing

Passes on one of its inputs, the one whose variant control is true: y = u_k. Each input has a control, a condition over the project's variables such as V==1, and the choice is made before the run from the variables' values then. The inputs that are not chosen leave the run, and so does every block that feeds only them.

Ports

• u1 … u_N – the choices, one per variant control. Add or remove inputs from the block's port settings, and keep one control per input. Each may be any size [m,n]: only the chosen one is read, so they need not agree.
• Output – y, the chosen input unchanged, of its size [m,n].

Parameters

• Variant Controls – one control per input, in port order, written as Simulink writes them, {'V==1';'V==2'}, or as a plain list, V==1; V==2. A control is a condition that is true or false: V==1, V~=1, V>=1 && V<=2, V==1 || W==2, mod(V,2)==1, or true and false. (default) marks the input taken when no other control is true. A bare name such as V is not a condition and is refused, as Simulink refuses it. The default is {'true';'false'}: the first input.
• Variant Control Mode – expression evaluates the controls as conditions; label treats each control as a name and takes the input whose name is Label Mode Active Choice; sim codegen switching takes the input whose control is (sim), and each control must be (sim) or (codegen).
• Label Mode Active Choice – in label mode, the name of the chosen input. Unused in the other modes.
• Allow Zero Variant Controls – Off: a run with no control true is refused. On: with no control true there is no choice, and the block leaves the run with everything after its output, as Simulink removes it.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It does not cross to Simulink, whose block has no rate parameter.

When a run is refused

In Simulink's words: no control true (must have at least one active port), more than one true (must have only one active port), two (default) controls, a bare name, a variable the project does not define, a value that is not true or false, and a number of controls that is not the number of inputs.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The choice is made before the export, so the generated body is a plain copy of the chosen input and holds no condition; the inputs not chosen, and what fed only them, are not exported. Re-export after changing a variable a control reads. The HDL targets are fully synthesizable.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/Variant Source. Variant Controls crosses as the cell VariantControls, which is what sets Simulink's input count; Variant Control Mode, Label Mode Active Choice and Allow Zero Variant Controls as VariantControlMode, LabelModeActiveChoice and AllowZeroVariantControls. The activation time is written as update diagram, the only one ICore makes; a model with another is reported on import. The rate does not cross.

Notes

• Algebraic, with no state: the output depends only on the current input.
• A block that reads this one's output and also something else keeps running when the output is removed, and reads 0 from it, as in Simulink.
• Controls name variables of the project's variables space; Simulink's Simulink.Variant objects and model workspace are not carried.
• To choose by a setting rather than a condition, use Signal Routing / Manual Variant Source; to choose on a signal, use Signal Routing / Multiport Switch.