Variant End — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Variant_End · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Variant End
Control Systems / Signal Routing
Closes a variant region a Variant Start opened: it passes on one of its inputs, the one on the branch the Start chose, y = uk. It has no controls of its own. It pairs with the Variant Start at its level whose Variant Start End Tag is its own, and the inputs not chosen leave the run with every block that feeds only them.
Ports
- u1 … uN – one per branch, in the order of the Start's outputs: input k is the end of the branch that leaves the Start's output k. Give it as many inputs as the Start has outputs. Each may be any size [m,n]: only the chosen one is read.
- Output – y, the chosen input unchanged, of its size [m,n].
Parameters
- Variant Start End Tag – the name that pairs this block with its
Variant Start, which must be at the same level. Default
A, as in Simulink. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It does not cross to Simulink, whose block has no rate parameter.
When a run is refused
In Simulink's words: no Variant Start of the same tag at this level (has no paired Variant Start block present in the current hierarchy); and whatever refuses the paired Start. ICore also refuses an End whose input count is not the Start's number of controls, and two Variant Starts of the same tag at one level.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The generated body is a plain copy of the chosen input and holds no condition; the branches not chosen are not exported. The HDL targets are fully synthesizable.
Simulink bridge
Import and export, mapped to simulink/Signal Routing/Variant End.
Variant Start End Tag crosses as VariantStartEndTag. The input
count is not a parameter in Simulink: it follows the paired Start's controls, and
an import gives the End as many inputs as its Start has outputs. The rate does not
cross.
Notes
- Algebraic, with no state.
- A block that reads this one's output keeps running whichever branch is chosen; only the branches leave.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Variant_End |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Variant_End |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Variant_End/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Variant_End.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Variant_End/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Variant_End.h |
| default size on canvas | 80 × 90 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u1 |
| 2 | in | ICoreDouble | u2 |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Variant Start End Tag | A | VariantStartEndTag |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Variant End |
| port-count rule | PortsParam::VariantEndInputs |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| deliberately not crossed | VariantPairedBlock |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Variant Start End Tag | VariantStartEndTag | passes through |
Caveat (shown to the user): the input count follows the paired Variant Start's controls on both sides; the pair crosses as
VariantStartEndTag; the block has NO SampleTime parameter, so a rate set here does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 3 ports (2 in, 1 out), and the 2 they cover does not reconcile — grouped, or one undocumented? a reader must sayB0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Variant End -- closes a variant region: the branch its Variant Start chose The Variant Source's shape, with no controls of its own. Measured on R2026a (FEATURES_TO_ADD.md §F.BF3 (e)): N in, 1 out, its input count following its paired Start's
VariantControls; one parameter,VariantStartEndTag(default 'A'); no SampleTime; alone it is Simulink:VariantLangBlocks:VariantStartBlockMissing, "Variant End block '...' has no paired Variant Start block present in the current hierarchy." The pairing, the choice, the pruning and the ten generators are ICoreVariantBlockBase's.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.