Switch — Control Systems/Signal Routing

Control_Systems/Signal_Routing/Switch · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Code facts#

Ports#

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#

Caveat (shown to the user): the three criteria map 1:1 onto Simulink's; the output type does NOT cross, because this block's output is always a 64-bit float where Simulink's Switch gives back the type it was given -- put a Data Type Conversion after it if an integer type has to continue

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Switch -- pass the first input or the third, decided by the second ALL FOUR PORTS ARE DECLARED AS 64-BIT FLOATS, AND EACH OF THE THREE INPUTS ACCEPTS ANY NUMERIC TYPE -- so a boolean, integer or floating-point link may land on any of them, including the control. Declaring the control port boolean instead would have made every diagram using this block non-exportable to the three hardware-description targets, because those carry every signal in one fixed-point format and do not yet apply a signal's type to it; the refusal is a property of the whole diagram, not of one cell. A switch is a comparison and a multiplexer, which is the one thing a fixed-point datapath does natively, so surrendering that permanently to spell a default differently would be a poor trade. The header carries the argument in full.

ONE CRITERION, THREE SPELLINGS, TEN LANGUAGES. The three criteria are a comparison against a threshold or a test for non-zero; each generator asks one shared helper in this file for the condition in its own spelling and drops it into its own select, so the rule is written once.

THE BLOCK NEVER ROUNDS ITS OWN OUTPUT: it chooses a value and stores it, and the output port applies its type once, as on every block.

Sample results#

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.01 · 60 steps · commit 31d36c2c3 · produced by docsSample --out <folder> --blocks Bus_Creator,Bus_Selector,Logical_Operator,Relational_Operator,Bitwise_Operator,Switch --steps 60 · data docs/generated/samples/Control_Systems__Signal_Routing__Switch.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).