State Writer — Control Systems/Signal Routing

State Writer

Control Systems / Signal Routing

Replaces the state of another block, named by its path, with its input, with no wire between the two: a Unit Delay’s held sample, a Delay’s line, an integrator’s accumulator, a state-space block’s x. The owner’s next step starts from what was written – a reset from anywhere in the model.

Ports

• Input u – the value written: one value, which fills every element of the state, or one value per element in the owner’s shape (a Delay of length N on a scalar takes a [1xN]; a state-space block’s x may be given as a row or a column). Any other size is refused before the run.

Parameters

• State owner block – the full path of the block whose state is written, as the navigator shows it (Home/A/UD). It follows the block when that block is renamed or moved. Owners: Unit Delay, Delay, Discrete-Time Integrator, Discrete Transfer Fcn, Discrete State-Space, Integrator and State-Space; any other block is refused with Simulink’s words (Block of type … cannot be a state owner block).
• State name – which of the owner’s states; empty (the default) names its one state, which is every owner’s only one.
• Sampling Time (s) – zero or less runs it whenever the subsystem it sits in runs, which is how Simulink’s State Writer takes its rate.

Where it may sit

As in Simulink, the writer and its owner may not share an order the model does not state: placed beside its owner, in the same subsystem, or in another subsystem with nothing ordering the two, the run is refused before its first step with R2026a’s message; so are two accessors of one owner in one subsystem. The placement that runs is the owner and the writer in two action subsystems of one If or Switch Case: on the steps the writer runs, the owner is idle, and it resumes from the written state.

Code export

Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text: the input is copied, element by element, into where the owner’s own code keeps its state in the generated core – in the three HDLs as a registered write, which the owner sees on its next clock (in Rust and C++ the core’s step does the copy at this block’s place, since a block there reaches only itself). A Discrete Transfer Fcn owner is refused by name: its export keeps input and output histories, not the state this block writes. So is an owner or writer inside a reusable subsystem function.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/State Writer. State owner block ↔ StateOwnerBlock: the path crosses relative to the subsystem exchanged and is written as the full path Simulink requires, set once every block exists (Simulink checks the block is there); an owner outside the exchanged subsystem cannot cross and is reported. State name ↔ StateName. "Sampling Time (s)" does not cross: Simulink’s State Writer has no SampleTime parameter and takes the rate of the subsystem it sits in.

Notes

• Measured on R2026a: an Integrator in an If’s action subsystem, written 0 from the else subsystem while it is idle, resumes from 0 – the idle interval is not integrated.
• Two writers of one owner on one step: the last one to run wins, with no diagnostic.